Design
of Sustainable Computing Environments
Subtitle:
Driven by the need to reduce the total cost of ownership
Chandrakant
D. Patel, HP
Fellow and Director, Sustainable IT Ecosystem Laboratory, HP Labs
Abstract: Continued population
growth coupled with increased per capita consumption will soon require
the creation of a new generation of cities in emerging economies and
around the globe. These cities will be driven by a growing desire for
on-demand, just-in-time access to critical resources at affordable
costs. Coupled with the increased risks that physical growth places on
the carrying capacity of the biosphere, we cannot expect to meet the
future needs of society simply by extending the existing
infrastructures.
We propose that the necessary
transformation be enabled by a global IT ecosystem made up of billions
of service-oriented client devices and thousands of data centers. The
IT ecosystem, with data centers at its core, and pervasive measurement
at the edges, will need to be seamlessly integrated into future
communities to enable need-based provisioning of critical resources.
Such a transformation of the IT ecosystem necessitates addressing
sustainability of the IT ecosystem itself from a cradle-to-cradle
perspective – minimizing the available energy needed for
extraction, manufacturing, waste mitigation, transportation, operation
and reclamation. This lifecycle based engineering and management will
result in achieving a reduced Total Cost of Ownership (TCO) of the IT
ecosystem that will serve the billions.
About the author:
Chandrakant Patel is currently an HP Fellow and Director of
the Sustainable Information Technology Laboratory at Hewlett Packard
Laboratories. Chandrakant has been a pioneer in microprocessor and
system thermo-mechanical architectures, management of available energy
as a key resource in “smart” data centers, and most recently,
application of the IT ecosystem to enable a net positive impact on the
environment. Chandrakant enjoys teaching, and has taught computer aided
design at Chabot College for 16 years. He also teaches courses in
thermal management at U.C. Berkeley Extension, Santa Clara University
and San Jose State University. Chandrakant has been granted over
100 U.S. patents, several pending. An IEEE Fellow, Chandrakant holds a
BSME from U.C. Berkeley, MSME from San Jose State University, and is a
licensed professional mechanical engineer in the state of California.
Rajesh Gupta, UC
San Diego
Abstract: Efficient generation, storage and use of energy is at the center of "Green Tech" today. To the extent, CANDE audience will allow it, this talk is a careful construction that looks at energy use at the scale of a small city, while avoiding the socio-political dimensions of sustainability. Specifically, we examine the issues associated with energy efficient buildings, building archetypes and their energy footprints from large scale monitoring and collection of longitudinal data. Based on our experiments, we attempt to outline what is realistic and possible with the emerging technologies that make combined optimization of energy use in buildings, and its relationship to the Water resources.
About the speaker: Rajesh Gupta is a
professor of computer science and engineering at UC
San Diego, and holds the QUALCOMM endowed chair in embedded
microsystems. His research interests are in energy efficient systems
that have taken turn towards large-scale energy use in recent years. He
directs smart buildings/smart grids task force at UC San Diego in his
role as associate director for the California Institute for
Telecommunications and Information Technology (CalIT2). He is
Editor-In-Chief of IEEE Embedded Systems Letters. He is a fellow of the
IEEE.
We are all familiar with devising
algorithms to find optimal or
near-optimal solutions to combinatorial problems. Whether these
solutions will
stand the test of time or whether the problems will remain relevant are
much
harder questions to answer when the research is being conducted.
This
talk will define the Optimal Research Problem (ORP), in which a
research problem
with maximum future impact has to be chosen given limited knowledge and
obeying resource constraints. We attempt to prove a hardness
result for
ORP, and attempt the development of heuristics for ORP.
Affiliation | Supervisor | Presenter |
Topic |
|
Colorado State U | Prof. Sudeep Pasricha | Shirish Bahirat | Hybrid Nano-photonic-electric On-chip Comm Architecture | |
Michigan Tech | Prof. Hu Shiyan | Jia Wang | Timing driven buffer insertion for carbon nano-tube interconnect and copper interconnect | |
U of Michigan | Prof. Igor Markov | Jarrod Roy | Hardware IP protection and anti-piracy | |
U of Cincinnati | Prof. Ranga Vemuri | Hao Xu | Aggressive Runtime Leakage Control in DSM CMOS | |
U of Utah | Prof. Priyank Kalla | Christopher Condrat | Logic Synthesis using optical devices | |
U of Virginia | Prof. Mircea R. Stan | Adam Cabe | Reliability Sensor Distribution using Scan Chain Insertion | |
Zhenyu Qi | MSN: Memory Sensor for NBTI | |||
UC Berkeley | Prof. Jaijeet Roychowdhury | Chenjie Gu | Non-linear projection based model order reduction for circuits and bio-chemical systems | |
UCLA | Prof. Jason Cong | Guojie Luo | 3D Physical design flow and 3D physical hierarchy exploration | |
Yi Zhou | Parallel Multi-level Analytical Global Placement on GPU | |||
UIUC | Prof. Martin Wong | Yan Tan | Printed Circuit Board Routing Is Calling for DA Help | |
Hongbo Zhang | Process-Aware 1-D Standard Cell Design | |||
Virginia Tech | Prof. Patrick Schaumont | Abhranil Maiti | Hardware enabled methodologies for protection of software IP | |
Prof. JoAnn Paul | Mwaffaq Otoom | Defining and designing Multicore workload specific processors | ||
UT Austin | Prof. David Pan | Duo Ding | CAD Optimizations for On-chip Integration of Silicon Nano-photonics | |
UC Riverside | Prof. Sheldon Tan | Thom Jefferson Eguia | General Behavioral Thermal Modeling and Characterization for Multi-core Microprocessor Design | |
Penn State U | Prof. Xie Yuan | Xiangyu Dong | System Level Performance, Energy and Area Estimation for PC-RAM Array | |
Université Bretagne Sud | Prof. Philippe Coussy | Ghizlane LHAIRECH-LEBRETON | Low Power High Level Synthesis for Designing DSP Applications on FPGA |