Topics:
The next CANDE workshop will be held on Thursday-Saturday,
April 10-12, 1997
at the
Rim Rock Hotel, near Banff.
Market forces are requiring that designers spend
less and less time in the total design cycle.
Unfortunately, one of the first tasks that are
eliminated is the evaluation of new tools or
methodologies that might help in the design process.
We've all been there. We develop a new wiz-bang
tool that we believe will have dramatic
effect on the speed/quality/size etc. of the
chips being designed. But we just can't get the
attention of the leading designers to give us
feedback on it's usefulness.
In this session, we'll hear from a group of
designers and corporate CAD managers on how they
are addressing this area. Clearly designers
can't affort to ignore new tools that might actually
help them. We all hope to learn how we can
help them in their review process by designing the
tools to be easier to investigate.
The speakers are:
Tentative: Simon Wong will discuss issues in deep-submicron
circuits. If you have a question or
problem for discussion, please send it to Wojciech Maly (maly@ece.cmu.edu).
Concept: If we are going to make use of 20 million transistors per
chip, we will need to build systems that make use of lots of memory.
That pushes systems-on-chips toward more software content. The
session would generally see the state-of-the-art in software design
as compared to CAD. Discussion would focus on barriers to introducing
more software content in systems-on-chips and multi-chip systems.
Topics/speakers:
Date and site
Workshop schedule
Session summaries
Reduced design cycle time and its impact on tool selection
Deep-submicron and scaling
CAD for software