CANDE '98

Next CANDE meeting: April 19-21, 1998

Sea Palms Golf and Tennis Resort, St Simons Island, Georgia

Sponsored by: IEEE Circuits and Systems Society

Topics:

Secretary's summary of CANDE '98 workshop.

Advance Program

Sunday, April 19: Evening reception

Monday, April 20: 9-9:15; Greetings; Discussion of projects for possible CAS sponsorship

Speakers/presenters:

Monday, April 20: 9:15-noon: Integrated Microsystems: The True Systems-on-Chips?

Organizer: Randy Harr

This session covers Integrated Microsystems (IM's), which include transistors and micromechanical devices. The question is whether this combination of technologies will open up significant new single-chip application areas in the future. The following are the speakers and topic areas:

Monday, April 20: lunch time; Continued discussion of projects for possible CAS sponsorship

Speakers/presenters:

Monday, April 20: Dinner session

Steve Domenik has agreed to arrange for a dinner speaker(s) relating to venture capital's vision of the future of the industry.

Tuesday, April 21: 9 AM-noon: Reconfigurable Computing: Niche or Mainstream?

Organizers: Al Dunlop and Randy Harr

This session covers reconfigurable computing (both FPGA and non-FPGA based techniques).

CANDE '98 Registration Information

Dates: April 19-21, 1998 Sea Palms Golf and Tennis Resort, St Simons Island, Georgia

To register for CANDE, print a copy of this form, fill it out, and mail it with a check (made out to IEEE CANDE) to:

Colleen Matteis
553 Monroe Street
Santa Clara, CA 95050
colleenmatteis@juno.com
(408) 296-6883 home or after 5 P call (408) 985 8058
The deadline for registration is March 13, 1998. Sorry, but we cannot take registrations by email.
The workshop fee is $490 ($485 if you contribute one or more questions related to this year's session topics). This fee covers the workshop, two nights (April 19 and 20) at the Sea Palms Resort, and food and beverages at CANDE group functions. The added fee for a double-occupancy spouse/guest is $140, which includes the room and all food and beverages at the group functions.

1998 CANDE Workshop Registration Form

Name:_________________________________________________________
Affiliation:______________________________________________________
Address:_______________________________________________________
______________________________________________________________
Phone:_________________________________________________________
Fax:___________________________________________________________
Email:__________________________________________________________
Please check all applicable options and compute the workshop fee:
___ Register me ($490 without questions)
___ Will bring spouse (double occupancy) ($140)
___ Need smoker's bedroom ($0)
___ Need extra nights - contact Colleen directly for availability
___ Provide one or more good questions relating to the topics (-$5)
Total amount: _____
My contribution to the pool of questions:

Proposals for CAS-Sponsored Projects

Allen/Terman Proposal

Proposal to the CAS Society for Support for the Development of an

Interactive Learning Environment (ILE)

for MOS Digital VLSI Design

****

Jonathan Allen and Chris Terman

Massachusetts Institute of Technology

May, 1988

 

1. Motivation and Vision: What do students need in order to learn how

to design MOS integrated circuits?

 

1.1 Students need textual material that describes and explains CMOS

digital integrated circuits and their behavior. By using hypertext,

the user can read the text "non-linearly", easily jumping to what-

ever textual materials are of interest. By providing access to the

text through a web browser, much supporting material can be readily

included, so that students can pursue particular topics in depth.

Direct links to journal articles provide close ties to current

research, and downloadable updates keep the text up-to-date.

1.2 In order to understand and design MOS digital integrated circuits,

we believe that the circuit schematic representation is central.

Because the circuits are digital, they are nonlinear, so that the

circuit equations can't be solved in closed form, and accurate

circuit simulation is essential to investigate circuit behavior.

Even simple circuits, with a few transistors, can display behavior

that is difficult for students to understand. For this reason, the

ILE provides a learning environment where for every circuit schem-

atic of the text (as well as any other schematic) the dependence

of circuit waveforms on topology or device parameters can be

investigated using a schematic editor and SPICE-like simulator.

Once a circuit schematic has been investigated and tuned, the ILE

provides a layout editor (with "real time" design rule checking) so

that the circuit can be realized in a practical technology. In

addition, the netlist corresponding to the layout can be extracted

and compared with the netlist corresponding to the circuit-level

schematic.

1.3 The interactive learning environment (ILE) that we are building

provides students with an integrated set of resources where they

can develop their understanding of MOS circuits through text

explorations coupled with an easy-to-use set of CAD tools which

facilitate the investigation of these circuits. In this way, the

student can develop hands-on experience in circuit design, and

build a confident understanding of circuit behavior.

1.4 In order to make the ILE universally available, it is being

implemented on the World Wide Web, so that it can be run on any

platform using a web browser. The CAD tools are written in JAVA,

thus avoiding problematic installation and upgrade procedures.

1.5 The ILE provides tutorial examples so that engineers can explore

the design space of possibilities for a given task, learning what

works best. The ILE provides an easy-to-use readily available

workbench where many such experiments are simple to conceive and

carry out.

 

2. Audiences for the ILE:

2.1 The ILE can provide both the text and laboratory environment for

traditional MOS integrated circuit design courses. Many electrical

engineering courses need a basic set of CAD tools which students

can use to create and analyze designs, often as part of a directed

laboratory exercise. Making the same tools available outside the

lab encourages students to undertake their own design efforts.

2.2 Distance education. Educational institutions are looking for ways

to export their learning experiences to people who can't attend

campus classes. By providing both the text and laboratories on the

web, courses can be pursued from virtually any location.

2.3 Life-long Learning. Most professionals aren't afforded the

opportunity to renew their skills by returning to a university

campus. Using the ILE, a wide range of educational experiences

can be provided over the web, including refreshers on basic

techniques, interactive primers on new technologies, and

downloadable examples.

 

3. Proposed Further Development of the ILE

3.1 Previous work and current status:

For the past 12 months we have been working on a prototype of

the Interactive Learning Environment using material from MIT's

graduate-level course "Introduction to VLSI Systems." We are using

the ILE to provide both explanatory text and a sequence of tutorials

where students use the ILE CAD tools to first understand and then

modify circuits designed to illuminate various issues in MOS VLSI

system design. Our goal is to have the students use the same CAD

tools to design a substantial end-of-term project. This project

not only lets students exercise their newly acquired circuit design

skills; it also exposes them to specific CAD tools and the central

role of CAD in the design process.

The need to support the design of a substantial project has led us

to use industrial-strength CAD algorithms and to provide a fairly

complete suite of tools: schematic entry, netlist generation,

circuit simulation, layout, netlist extraction, and layout-vs-

schematic network isomorphism.

The work we propose here uses the current ILE prototype (as demon-

strated on April 20, 1998, at the CANDE meeting) as a starting

point. We next plan to finish the implementation of the schematic

entry system and the circuit simulator (see the first Milestone

below). Much of the basic mechanism has already been implemented

and the remaining work should go relatively quickly. For the second

milestone we propose to implement a "Magic-like" layout editor

incorporating a "real-time" design rule checker. We're familiar

with the Magic implementation and have already completed implement-

ation of the tile-based database and the basic tile manipulation

operations. Finally, in our third milestone, we propose to provide

a sample environment based on our introductory VLSI design course.

3.2 Milestone 1: Schematic Entry and Simulation (Fall '98)

Hierarchical schematic editor

Libraries of basic components

R, L, C

indenpendent and dependent voltage and current sources

mosfets, diodes

simulation interface including probes and ammeters

CMOS gates

SPICE netlist generation

SPICE-like circuit analysis program

modified nodal analysis using sparse matrices and LU decomposition

mos models

IDL models: levels 1 and 3

voltage-dependent diffusion capacitances

Meyer gate capacitance model

DC and transient analysis

automatic time-step control and convergence checking

Simulation waveform browser

Printing of schematics and simulation output

ILE website

tool download

schematic and simulation documentation

schematic and simulation examples

3.3 Milestone 2: Layout tools (Summer '99)

Hierarchical layout editor

tile-based layout database (like Magic)

real-time DRC

technology file for process-specific information

Netlist extraction

Netlist comparison (LVS)

GDS/CIF file import/export

ILE website

layout documentation

layout examples

3.4 Milestone 3: A demonstration Interactive Learning Environment

(Fall '99)

course notes and figures from MIT's "Introduction to VLSI Systems".

tutorial examples drawn from each of the chapters

a sequence of design problems with sample solutions

 

4. Budget:

In order to complete the work outlined above, we are requesting

$350k (including loading). Most of the cost is for salaries, but

there are a variety of materials and supplies that we will need, and

we would like to have some travel funds to demonstrate the system at

appropriate meetings. Deliverables include the total ILE as a web

site, with documentation, and we can also make the entire system

available on a CD-ROM, which will make the ILE useful for those

using a laptop platform without web connection. We believe that the

proposed system will be very useful in academia and industry, and

that use of the ILE will deepen designers' understanding of MOS

circuits, and the ways in which their performance can be optimized.

 

5. Comments and questions can be referred to either of us:

Jonathan Allen, MIT 36-413, Cambridge MA 02139

tel: 617-253-2509, fax: 617-253-1301. email: jallen@mit.edu

Chris Terman, MIT NE43-636, Cambridge MA 02139

tel: 617-253-6038, email: cjt@lcs.mit.edu

 

Kathy Preas Proposal

Proposal: Converting and Updating The Design Automation Library

Overview

------------

In 1992 SIGDA published the Design Automation

Library (DALibrary, or DAL), consisting of conference

proceedings from the major design automation conferences

(EDAC, DAC, ICCAD, ICCD) and Transactions on CAD from 1964-

1990. The material was keyed, a search engine provided, and

each page was scanned. Thus the entire contents of each

proceedings and journal was available to the user.

In 1994, SIGDA began the CD-ROM Project, which aimed to take

electronic input directly from authors of conference papers

and transfer the papers to CD-ROM in time for the conference

proceedings to be available on CD-ROM at the conference. At

the end of each year, all proceedings are then combined into

a compendium CD-ROM, with a search capability.

The years between the last volume of the DALibrary and the

beginning of the conferences on CD-ROM Project (1991-1993,

inclusive, and 1994 ED&TC) have come to be called "the

missing years" and much discussion has taken place about

making this material available, either on CD-ROM, over the

World Wide Web, or both. Additionally, the original DAL

search software is outdated.

Goal of the Project

---------------------------

The goal of this project is to provide rapid, on-line access

to DA literature published in conference proceedings and

journals. The main goal is to make this material available

over the WWW. CD-ROMs are also possible.

As a long-term goal, the participating societies will work

toward making all design automation literature freely available

over the WWW. This may occur after the literature has

reached a certain age, for example, 3 years after original

publication, depending on the policy of the copyright holder.

Project Plan

------------------

The Missing Years

This project will capture the material from the

missing years by keying of the text to HTML and

scanning page images to PDF.

SIGDA has already begun to capture the material from the

Missing Years. HTML files and PDF page images of

DAC 91, 92 and 93 are currently being edited and indexed

for posting on the SIGDA Web site. (See

https://jamaica.ee.pitt.edu/DAC/28dac/main_ss.htm

for a first draft of DAC91.) Capture and keying

specifications are in place with a data capture company

(PacificData Conversion Corp.).

Conversion of DAL

The DAL material is in a very different format from that

proposed for the missing years, and the search software

cannot be updated. It is proposed that the material be

converted into HTML and PDF images. Funding

for a student to work on this issue is proposed.

Proposed Schedule

-------------------------

*Year 1 - one-half of the Missing Years capture and index (7

volumes); hire student to work on conversion (see Appendix 3);

*Year 2 - one-half of the Missing Tears capture and index (7

volumes); one-fourth of DAL conversion edited and indexed;

*Year 3 - one-fourth of DAL conversion edited and indexed

*Year 4 - one-fourth of DAL conversion edited and indexed

*Year 5 - one-fourth of DAL conversion edited and indexed

Budget

-------------------------

To key, scan and index material from 1991-1994:

key+scan index

-------- -----

Year 1:

ICCAD - 3 years - $15,000 + $12,000 = $27,000

TrCAD - 4 years - $40,000 + $16,000 = $56,000

---------

$83,000

Year 1:

ED&TC - 4 years - $20,000 + $16,000 = $36,000

Euro-DAC - 3 years - $15,000 + $12,000 = $27,000

--------

$63,000

Total Missing Years Cost $146,000

To convert DAL material to HTML and PDF images:

Funding for a student to work on conversion: $25,000

Indexing of all DAL material: $212,000

-------

Total DAL Update Cost $237,000

Total for Missing Years and DAL Update $383,000

Summary of Cost Projection

--------------------------

Year1 Year2 Year3 Year4 Year5

Function:

Miss. Yr.

---------

ICCAD $27K

TrCAD $56K

EDTC $36K

EuroDAC $27K

DAL Update

----------

Programming

Extraction $25K

Indexing

1990-88 (13 vol) $52K

1987-85 (12 vol) $48K

1984-80 (12 vol) $48K

1979-64 (16 vol) $64K

----------------------------------------------------------

$108K $115K $48K $48K $64K $383K

CDROM Production:

Cost of $2/disc, plus $1,000 per CDROM title, plus shipping. Number

of discs required will probably be similar to DAL.

Who Does What?

-------------------------

Preliminary approach -

KP: organize, finalize file structure;

QA material from service bureau;

contract with service bureau;

monitor progress, manage contract

workers and QA the results.

Service Bureau: scan pages to PDF, capture text in

HTML with links to scanned pages

CAS: obtain permission for republication

of material from IEEE (copyright

holder)

aid in obtaining 1990-1994 volumes

student work on conversion project

contract workers create DAL indexes

Submitted by

Kathy Preas,

SIGDA CDROM Project Administrator

------------------------------------------------------------

KP Publications on CDROM

151 Cowper Street +1-650-325-0848 - phone

Palo Alto, CA 94301 +1-650-325-1106 - fax

email: kathy@cse.psu.edu or kathy@ee.pitt.edu

------------------------------------------------------------

Appendix 1 - What is involved in capturing the Missing

Years?

------------------------------------------------------------

The project can be divided into the following tasks:

*Organization and Planning

Generate preliminary design [done]

WWW, CD-ROM, or both?

how to handle front matter

coding - HTML, specify codes

search engine

how to handle text, PDF (?), PS in Table of Contents,

etc.

Collect the relevant literature (3 copies of each volume)

ED&TC, EURO-DAC, ICCAD, TrCAD

Investigate data conversion contractors (OCR and keying)

and their capabilities [done]

Coordinate with ACM and IEEE

Copyright permissions

*Develop Design Specifications [done]

Scanning specs

Capture specs

Mock-up of design

Technical project plan

*Develop budgets and schedules [done]

Financial project plan & schedule

Cost of scanning, keying

Cost of indexing

*Capture Text and Figures [done for DAC 91, 92, 93]

Negotiate contract

Test runs

Preliminary version on WWW

Actual Capture

Link text and figures

*Assemble Material [dac 91, 92, 93 - in progress]

Generate TOC, AI, FM, data structures

QA

Appendix 2 - The Missing Years: Page Count

------------------------------------------

The number of pages in the missing years is:

1991 1992 1993 1994

_____________________________________________

ED&TC 601 572 ? 684

DAC [done]

Euro-DAC ? 766 ? X

ICCAD 579 639 789 X

TrCAD 1585 1586 1983 1568

Appendix 3 - Tasks for DAL Conversion

-------------------------------------

*Develop a program to convert the SGML test into HTML

*Develop a program to convert page images into PDF

*Write a script to extract Table of Contents, Author

Index, and Abstracts from HTML

The proposal is to hire a student to accomplish these

tasks.

TOC, AI and Abstracts must be edited and links to page

images added. I hope to be able to contract some of this

work out, as it is very time-consuming (up to 100 hours

per volume).

 

Shaw Project

 

CANDE/CAS PROJECT PROPOSAL

C. A. Shaw, May 5, 1998

 

IDENTIFICATION OF INHIBITORS TO FULL WWW USE BY WORKING ENGINEERS

 

PURPOSE: The first phase of a multi-phase project to facilitate the use

of the WorldWide Web by working circuit designers and CAD developers.

This phase studies current use, identifies inhibitors and proposes

projects to remove them. Follow-on phases develop solutions to these

inhibitors.

 

DURATION: One academic year - September to April

 

METHOD: Undergraduate seniors in Electronic Engineering and CAD major

programs, who are interviewing with prospective employers are also

funded to survey a number of working engineers and CAD professionals in

these companies on their Web usage and reasons for not making full use

of the Web. The survey results are correlated into a report by these

students before graduation.

 

FINANCING: A senior advising professor at each university selected would

be funded to carry out the study, and would determine the distribution

of funds among the participating students and his/her own participation.

To insure completion of the study, 25% of the funds would be delivered

only on submission of the report.

 

COST: $10,000 per university selected is the estimate. Preferably,

2-3 universities would be selected, for a total cost of $30,000.

 

DISCUSSION: Undergraduate seniors typically will have very extensive

knowledge of the Web and its content through use in their undergraduate

program. Since they are travelling to various companies in their job

search, this added activity can be carried on with little additional

expense. It also should intrigue some of the companies they visit. Care

would of course be required to remove any identification of individuals

and companies in the report on each individual interview. Students would

be required to search out a variety of people in different jobs and

disciplines, ranging from junior designers to senior R&D managers, from

R&D to Manufacturing to Quality to other disciplines.

 

COMMITMENT: The DAC-source of funding for these grants requires that it

not establish a committed continuing program. This meets that

requirement, since the decision to select follow-on projects can be

completely divorced from this requirements study.

 

PROJ. MGMT: I will accept to run this project if it is approved.

 

SEQUENCE: If approved, through the summer I would send out "requests to

bid" using such methods as Don Bouldin's email notices, postings to

various newsgroups, etc. All interactions can be by email, phone and

fax, no travel should be required.

 

As the studies are started, I would contact the faculty leader at

each university at regular intervals to assure that progress was on

schedule. I would submit a final report, and the results of each

university's survey, to CANDE. I would suggest follow-on projects to

CANDE and CAS, following normal procedures.

 

 

Grout et al. Project

CANDE Proposal to Circuit and Systems Society for Support of the Acquisition and Development of Advanced EDA Benchmark Data Sets Needed for the Development and Research of High Performance EDA Applications (AEBM)

 

CANDE Proposors:

Steve Grout (SEMATECH)

Dr. Chuck Alpert (IBM)

Dr. William Joyner (SRC)

Dr. Farid Najm (University of Illinois)

May 6, 1998

 

 

Abstract - Proposal Executive Summary:

This is a CANDE proposal requesting Circuit and Systems (CAS) Society support acquiring and, where applicable, development of challenging new Advanced EDA Benchmark Datasets (AEBM or 'abe'-'em') needed by industry to further the research and development of important EDA applications. The need for challenging EDA benchmark datasets has been previously identified by the NTRS94, SEMATECH, and elsewhere in industry as being critical to the development of high performance EDA tools and algorithms needed for both high end ASIC and high performance advance processor integrated circuits (APIC). While previous efforts produced only small and medium industry benchmark datasets, this proposal would build on the approach of a recent industrial success. Alpert (IBM), reporting at ISPD98, has produced benchmarks an order of magnitude greater complexity than existed before. More benchmarks are critically needed and they need to be an order of magnitude greater size and complexity. Funding this activity is expected to enable fresh new research leading to a critically needed new generation of high performance tools.

1. Introduction

Development of any product and application has always required testing based on realistic data. Due to the difficulty in fully characterizing design data, development of EDA tools has also benefited greatly from process of trying new tool approaches on a wide range of datasets and benchmarking new approaches against existing tools and algorithms. Benchmark results are also very vital to potential purchasers of EDA tools in projecting performance, capacity, robustness, quality, and cost.

1.1 Previous work

As documented in Alpert/ISDP98, Brglez/CBL is most notable for in the last 10 years bringing forward benchmark datasets and communicating their nature through numerous papers published at appropriate design automation conferences. Alpert/ISPD98 reviewed their size and characteristics in detail and objectively concluded that significantly larger and more complex benchmarks are needed. For instance, use of the existing benchmarks across different partitioning algorithms produced results within 1% of each other. Alpert noted that no new benchmarks have been introduced for 5 years. Technology moves fast. New benchmark circuits need to become available at least every 2 years or so to avoid algorithms that merely target the foibles of the existing benchmarks.

1.2 Motivation and Vision:

Separate from Alpert's work, a wide range of industry inputs were reflected in the SIA NTRS94.

NTRS94 identified the need for large complex benchmarks of state-of-the-art designs. It further notes that this is critical to the development of validated high performance and productive EDA tools needed for to produce upcoming leading edge ASICs and high performance advance processor ICs (APIC) at 250nm (0.25u) feature size and below.

 

In a short 5 years from now, APIC chip manufacturers must be ready for chip starts using 100nm feature size with at least 10X higher performance and more productive design process. It has been shown that not meeting that level of design capability will directly effect the overall profits of US and other chip manufacturers worldwide.

1.3 Current Status

Prior to Alpert/ISPD98, efforts to produce more challenging benchmarks were unsuccessful. This was primarily due to the fact that such datasets only exist in the target high-end APIC designs of highly competitive chip manufacturers. There was simply no way that any one manufacturer could see their way to taking the risk to release datasets that could expose their technology to competitors. A few benchmarks have existed that were very carefully shared between specific manufacturers and key EDA suppliers on an extremely controlled and limited basis, and only when there was a direct immediate need. Several EDA suppliers has tried to set up 'vault testing facilities' that correspond very much to those used the DoD suppliers. However, these approaches have not in any way opened up those benchmarks to general use by academia and the EDA supplier industry.

 

Alpert/ISPD98 describes a success within IBM where the IBM Austin Research Lab eliminated the "IP" aspects of group of large blocks through use of a parser that only extracted a controlled small fraction of the overall information. This effort resulted in moderately large hierarchical netlists used mainly for exploring much needed APIC partitioning improvements. This activity also took a highly focused effort within IBM to get wide range of management buy in to both the IP ‘elimination’ process and to balancing the benefit to IBM versus possible risk.

 

Having worked through his company’s concern about sharing design data as benchmarks, Alpert successfully put IP-cleansed datasets as industry benchmarks into the public domain that were an order of magnitude greater complexity and size than previously available.

 

We propose to follow and build on the process successfully used by Alpert.

1.4 Target Users of the benchmarks

The following are expected target users that will benefit from funding the acquisition of the proposed benchmarks:

1.5 Benefits to industry and academia

In summary, the expected benefits of funding this benchmark effort are:

2. Proposed Industrial and Academic Benchmark Acquisition Program

In this section, we describe this CANDE proposal for both the approach and use of requested funding for acquiring new industry benchmark datasets.

2.1 3 Phase Benchmark Acquisition Program

We propose a 3-phase program:

1) Joint Industry and Academia Planning done via an open workshop, resulting in detailed plans, commitments, identification of resources, and refining budgets, milestones, deliverables, and schedules.

2) Acquisition and limited generation of benchmark datasets, including some initial benchmark use for early validation of the characteristics of the benchmarks

3) Documenting and repositing of the benchmarks onto a freely accessible site.

2.2 Program Management

We propose that the program be managed at 2 levels

2.3 Phase 1 - Planning Workshop

We propose to initiate this Advanced EDA Benchmark Acquisition Program through a 2-day joint workshop involving invited key industry leaders such as from CAS, SRC, SI2, CANDE, IEEE, SEMATECH, EDAC, and other interested industry groups. The objectives and tasks of the workshop will be to explore, define and agree on program requirements, objectives, approach, review past approaches and results, review recent developments both with respect to both benchmark datasets and available benchmark-generation tools

 

We would seek to hold the workshop using facilities of an interested industry company, and request CAS funding to offset only any other unavoidable additional costs of running such a workshop. However, we expect to confirm that the workshop can be held without cost at an industry site prior to initiating the program. Announcements, communications, and planning for the workshop would be done without any funding by volunteers, making use of email and web based techniques. We would also anticipate setting up a no-cost web site on a facility such as EDA.ORG to provide industry access to information concerning program progress. (We would therefore follow the approach used for many ongoing EDA technical standards meetings.)

2.4 Phase 2 - Benchmark Acquisition and Generation Thrusts

Three approaches are proposed with modest funding requested for each. They are presented below in order of the expected return on funding investment, that is, starting with the potentially most useful expected results.

 

We request all three thrusts be funded as it is highly likely that we will be able to obtain only a limited number of useful, badly-needed, large benchmarks from industry and academia. The rest may have to be generated

2.4.1 Industry Benchmarks Acquisition Thrust

This activity would focus in two areas of acquiring benchmarks from industry datasets.

2.4.1.1 Expansion of the Current ISPD98 Benchmarks

This effort would be to provide two person months resource to be applied to expanding the current ISPD98 benchmark set to attempt to EDA applications in addition to partitioning such as the following:

 

This work would include formatting the ISPD98 into applicable standards. Tentatively, RTL netlists could be created and flowed down through synthesis, physical design, to mask out in order to capture the remaining dataset versions.

2.4.1.2 Acquisition of New Industry Benchmarks

This effort would be to provide 2 person months each to acquire benchmark data sets from 3 other high end ASIC and APIC design companies. These benchmark acquisition activities would be done using the same ISPD98 techniques to remove IP information from those benchmarks. The funding would be used to provide the direct manual processing needed and perform basic exercising of the benchmarks. This would validate the processing and reformatting and quantify them with respect to the same exercising done on the ISPD98 benchmarks.

 

The total requested funding level for this primary initiative is 6 person months.

2.4.2 Academic Benchmarks Acquisition Thrust

This effort would be to fund a limited activity of 2 person months each to reformat two existing chip designs within university programs for use as benchmarks. As of this writing, available chip designs include one developed previously by Dr. Don Thomas at CMU, Rutenbar's CMU 750,000 transistor DSP chip with synthesizable Verilog and expected mask data. Hennessey's FLASH at Stanford, Teresa Meng's work at Stanford, Brodersen's Infopad at Berkeley, and Abraham's University of Texas sizable VHDL models.

 

The total requested funding level for this university benchmark initiative is 4 person months.

2.4.3 Benchmark Generation Thrust

To back up the above benchmark acquisition efforts, we propose a limited activity in benchmark generation.

 

As of this writing, we are aware of only two efforts to algorithmically generate IP-neutral benchmark datasets from previously characterized datasets. These efforts include the work of Hutton/FPGA96 and Ghosh of Brglez/ISPD97. We propose to fund a modest 2-person month effort to evaluate those two tools against the ISPD98 benchmark datasets. Generated datasets will be evaluated for correspondence to the original ISPD98 dataset metrics and for partitioning performance using a subset of the tests run against ISPD98.

2.4.3.1 Further-On Benchmark Generation Research

It is anticipated that this benchmark development program may lead to prompting others to do additional benchmark generation research and development. At this time, our proposal does not include support

for such funding. Such interest will be reported to the program advisory body and to SRC for possible later consideration.

2.5 Phase 3 - Documenting, Online Repositing, and Wrapup

This effort would be develop minimal documentation, verification of the datasets formats, and inserting the benchmarks into an online repository. SRC, with review by the program's advisory body, would select a repository site to host these benchmarks. Resource funding would be 2 person months.

 

2.5.1 Program Wrapup and Futures

During this phase, with inputs from each of the program participants, SRC will create a brief final report summarizing the program's results and lessons learned.

 

 

3. Milestones, Deliverables, and Schedule

Detailed milestones, deliverables, and schedule would be defined as a part of the Planning Workshop held during the first phase of the program.

 

3.1 Milestones:

 

3.2 Deliverables:

 

3.3 Schedule:

4. Budget

 

In order to complete this CANDE-proposed Advanced EDA Benchmark Dataset Acquisition Program proposed above, we request funding support for 16 person months or $80K (based on an estimated $5K per typical person month).

 

All funding will be used to supply resources to industry and academia for direct use in acquiring the target benchmarks. Our approach focuses on providing funding for students preferably from ongoing university EDA research and development programs. The experience provided by their participation in this program would then provide some level of technology transfer of the acquisition process back into those EDA-related academic programs. We further anticipate that the students would also participate in the development and presentation of later technical papers on the benchmark acquisition process and use.

 

All other activity for this benchmark program be unfunded and is expected to supplied by those interested in getting and using the benchmarks. Computers, office space, supplies, etc. is expected to be provided by the cooperating design companies and applicable universities.

 

While we request agreement to fund the entire proposed program, funds will only be taken for those parts of the program for which we are successful in finding industrial and academic participants.

5. Questions and Comments

Comments and questions on this CANDE proposal can be referred to any of the proposors.

6. References

Alpert/ISPD98 - Charles J. Alpert. The ISPD98 Circuit Benchmark Suite. 1998 International Symposium on Physical Design, April, 1998

 

Hutton/FPGA96 - Michael Hutton, Jonathan Rose and Derek Corneil. Generation of Synthetic Sequential Benchmark Circuits . Proc. 5th ACM/SIGDA International Symposium on FPGAs, (FPGA 97), Feb., 1997.

 

Ghosh/Brglez/ISPD97 - Nevin Kapur, Debabrata Ghosh and Franc Brglez. Towards a New Benchmarking Paradigm in EDA: Analysis of Equivalence Class Mutant Circuit Distributions. 1997 International Symposium on Physical Design, April, 1997

 

APPENDIX: Comments on the Draft Proposal

 

The below are comments received as of 5/12/1998.

 

Some comments from Rob R. (rutenbar@ece.cmu.edu):

>This is basically a good idea. I wonder if you plan to limit

>this to supporting only industrial benchmark creation.

 

No but at the time last week drafting, I could only recall the chip

attributed to Don Thomas (CMU), hence the proposal version you received

only referenced that.

 

>We need these badly, but in almost all circumstances

>these get 'neutered' in some way before they go out.

>There are some large-ish university projects wherein

>the designs are complete, if a bit further from the

>leading edge. One might ask if these might also serve

>a purpose since they don't get sanitized as much--and

>if they were properly constructed we could reimplement

>them in more aggressive technologies as we get access.

>Example: some of my colleagues here at CMU

> are taping out in about a month

>a DSP chip with about 750,000 transistors. It's

>in synthesizable Verilog. They verify it by full

>mask-level extraction, and they run a full FFT code

>on the transistor-level netlist for 8 CPU-days per test,

>and measure power in Avanti Star-Sim. There has been discussion

>in turning this into a serious IP benchmark, but the

>question is: who would support the 6 mos of staff time

>necessary to get this into shape to be a usable,

>cleaned up benchmark? Would this qualify for this

>proprosed effort? There are other designs around like

>this: Hennessey's FLASH at Stanford, Teresa Meng's stuff at Stanford,

>Brodersen's Infopad at Berkeley, etc.

 

I think the best process is now

  1. mention the above 4 now as university candidates
  2. dig up the size/complexity of all 5
  3. expand the plan from 1 to 2 for the current funding request (that would make the overall plan 1 expansion, 3 new industry, and 2 university) – that would add $10K to the total requested.
  4. We would then go over the university-chip benchmark side of the program during the planning phase and work to what we conclude.
  5. expand the final step which suggests various universities submit white papers in anticipation of next phases for this benchmark acquisition activity.

 

>FYI, just some random thoughts... -rob

>--Rob A. Rutenbar

>Professor of ECE (and by courtesy, of CS)

>Director, CMU Center for Electronic Design Automation

>Dept of Electrical and Computer Engineering

>Carnegie Mellon University

>5000 Forbes Ave.

>Pittsburgh PA 15213

>Tel 412 268 3334

>FAX 412 268 2859

>email rutenbar@ece.cmu.edu

>secretary lyz@ece.cmu.edu

 

 

> Steve;

>

> . . . I just had one

> question about the list of EDA applications in section 2.4.1.1.

> Is this list meant to be "complete". If so, then there are a

> few things missing, such as test generation, fault simulation,

> signal integrity analysis, and many others. In fact, we should

> aim to have the benchmarks developed in a way that any/all

> possible EDA applications can make use of them.

 

The list was not intended to be complete and lord knows

we don't want to again have 'test be last'.

 

> If the list is not meant to be complete and, instead, is only

> for illustration purposes, then the proposal should probably

> say that, so that we are not held to supporting an incomplete

> list of applications.

 

Good correction. Will revise accordingly.

> Regards,

> Farid.

>

> =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

> * Farid N. Najm Associate Professor of ECE *

> * Email: najm@uiuc.edu Electrical and Computer Engineering Department *

> * Tel: (217) 333-7678, University of Illinois at Urbana-Champaign *

> * Fax: (217) 244-1946 Coordinated Science Laboratory, 1308 West Main St *

> * WWW: https://www.uiuc.edu/ph/www/najm Urbana, Illinois 61801-2307, USA *

> =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

 

------------------------------------------------------------------------------------------------------------

Verbal comments were also received from Dr. Sumit Dasgupta (IBM Austin Research Labs) and is reflected in the prsent proposal.

Justin Harlow (SRC) provided significant thoughtful comments about the overall approach, SRC relationship to the program, and managing program risk.

 Secretary's Report of CANDE '98 Workshop

 

CANDE '98 Workshop was hold at St. Simmons Island G.A. on April 19-21.

We had 36 attendees and workshop was very successful as usual.

 

We covered following three topics. You may see some of these presentation

on CANDE web site.

 

Topics 1) Integrated Microsystems < The true System-on-a Chip ? >

Organized by Randy Harr

Topics 2) Discussion of projects for possible CAS sponsorship.

Moderated by Wayne Wolf

Topics 3) Reconfigurable Computing < niche or Mainstream >

Organized by Al Dunlop and Randy Harr

Our dinner session speaker this year was Mr. Steve Domenik.

He spoke about venture capital's vision of the future of the industry.

Thanks again to the all speakers and moderators of these sessions for

their excellent talk.

 

We decided to continue discussion on the projects for possible CAS sponsorsh

ip at CANDE DAC meeting.

 

One of important discussion was the timing of CANDE workshop.

Some of CANDE members prefer CANDE workshop in fall rather than in spring.

Colleen Matteis explained difference of hotel reservation in spring and

fall( most case spring is harder and more costly).

After some discussion we did tentative vote. Result

 

1) Prefer Spring -- 7

2) Prefer Fall (September) -- 8

3) Doesn't matter -- 9

others are abstention.

 

If we will move the workshop in fall majority of the attendees

prefer '99 fall rather than '98 fall.

We continue to discuss this subject CANDE at DAC.

 

Other topics was the location of the next workshop. Wayne Wolf said

next will be on west of Mississippi without argument !

Some proposed locations were

1) Jacksonhole 2)Pismo Beach 3) Vancouver 4) Grand Canyon

5) Loveboat ? 6)Whistler Mountain 7) Sedona, AZ 8) Taos

We will discuss this subject at DAC CANDE meeting also.

You will receive formal DAC meeting schedule soon.

 

Please come and join CANDE meeting at DAC'98 in San Francisco (Wednesday, June 17, 6 PM).