| In this design, an Ambric¡¯s Massively Parallel Processor Array (MPPA), which includes 336 asynchronous processors and communicates through a configurable structure of channels with a 128-bit high speed (100MHz) Input/Output (I/O) port, is used to implement the 64-channel digital beamformer. Besides the beamformer, the system is composed of 256-channel analog front-end pulser/receiver, 64-channel of Time-Gain Compensation (TGC), 64-channel of high-speed digitizer, a host PC and a PCI Express-based accelerator in the Am2045 chip with a 512 Mbytes external memory. This system is designed to handle a 256 elements linear array or a 64 elements phased array transducer. The system provides 64 channels of excitation pulsers while receiving simultaneously at a 150 MHz sampling rate with 12-bit resolution. The digitized data from all channels of one frame are first stored in the internal memory of MPPA. The coarse delays are integer multiples of the sampling clock rate. They are achieved by dynamically updating the memory addresses which are loaded in the delay coefficients table. Random Memory Access capability of MPPA enables processors to randomly access data while it is still in channels, which eliminate the necessity of moving all data from I/O ports into memory before they can be processed. The fine delays are implemented by FIR filters with an interpolation factor of 8. This technique and architecture allow dynamic receive focusing, aperture growth, spatial filtering, and scan conversion by software only. |