IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

August 16, 2007

Mtg: An Alternative Method for Manufacturing Robust Electronic Assemblies Without Solder

by @ 7:02 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

WEDNESDAY November 14
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Joseph (Joe) Fjelstad, President, Verdant Electronics
Time: Optional dinner at 6:30 PM, Presentation at 7:30 PM
Cost: Dinner $25 (by Nov. 11); no cost for meeting
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: by email to Janis Karklins,

The electronics industry has assembled electronic components to printed circuit boards for more than 50 years. ? That relationship has been an enduring one, however with the transition from traditional tin-lead solder to new lead-free solders mandated by European legislation, the industry is being saddled with significant new expenses and plagued with problems not previously encountered. ? In this environment, an improved approach (more…)

Mtg: The Missing System of Nanoscale Education

by @ 2:03 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors

TUESDAY September 18
SCV Nanotechnology Chapter
Speaker: Dr. Nora Sabelli, Senior Science Advisor, Center for Technology in Learning (CTL), SRI International
Time: Registration & light lunch 11:30 AM; Presentation at noon
Cost: Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1, CMA Room, 2900 Semiconductor Drive, Santa Clara
RSVP: on our website

The nanoscience revolution brings together diverse areas of human endeavor including science, medicine, industry, and environmental management. It requires a commensurate response in the educational community to increase students’ understanding of core concepts in the field. The presentation (more…)

Mtg: Physical Design of SUN’s Niagara2 Processor

by @ 1:59 pm. Filed under ALL, Computers/Software, Electronics Design, Semiconductors

THURSDAY September 20
SCV Solid State Circuits Chapter
Speaker: Umesh Nawathe, Senior Manager at Sun Microsystems
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: Donation for food
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required

Niagara2 is the 1st 64-bit 64-thread SPARC ‘System on a chip’ from SUN based on the power-efficient CMT architecture optimized for Space, Power and Performance (SWaP). ? It is the successor to Niagara1, which is known in the market as the UltraSparcT1. (more…)

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