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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

September 19, 2007

Mtg: Cyber Security for the Electric Utility Industry

by @ 2:06 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power
 

MONDAY October 15
SF Power Engineering? Chapter
Speaker: Joseph Weiss, Task Force Lead, information security impacts on IEEE standards
Time: Light lunch and Presentation, Noon – 1:00 PM
Cost: Free for IEEE members, $5 for non-members
Place: Pacific Gas & Electric Office, 245 Market Street, Room 1417, San Francisco
RSVP: Required for admittance; to Shirin Tabatabai, sxth@pge.com, 415-973-1474
Web: www.e-grid.net/docs/0710-sf-pes.pdf

Joseph Weiss will discuss the NERC Cyber Security Infrastructure requirement.? He will discuss the critical connection between digital control systems, such as SCADA, and Americaâ??s infrastructure and how to protect these systems from intentional or unintentional cyber incidents. He will also discuss some actual case histories (more…)

September 17, 2007

Mtg: Early Reliability Testing

by @ 2:31 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY September 26
SCV Reliability? Chapter
Speaker: Mike Silverman and Arthur Zingher, Ops A La Carte
Time: Refreshments at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: HP-Cupertino Oak Room, Bldg 48, Pruneridge Ave. and Wolfe Rd., Cupertino
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/rl/events.htm

(Replaces earlier topic, “Structural Reliability Methods for Improved Designs Against Fatigue”). ? Almost every industry is competing on Reliability and therefore, there is a need to develop more reliable products faster. However, reliability testing and improvement often are performed when development is nearly complete, when the product is nearly frozen, when time is short, (more…)

Tour: Military Vehicle Technology Foundation Collection

by @ 1:10 pm. Filed under ALL, Communications, Electrical/Power, Electronics Design, Engineering Mgmt
 

SATURDAY October 6
SCV Product Safety Engineering + Vehicular Technology? Chapters
Time: 10:00 AM
Cost: none; limited to first 25 people, with priority to PSES and VTS members
Place: Portola Valley
RSVP: by email to Gary Eldridge, geldridge@apple.com, to reserve a spot and receive instructions
Web: www.e-grid.net/docs/0710-scv-pses+vts.pdf

We are pleased to announce a very special fall event! Join us on October 6 (Saturday) at 10:00 am for a specially arranged private tour of the MVTF (Military Vehicle Technology
Foundation) located in Portola Valley.? This will be a rare opportunity (more…)

September 14, 2007

Event: Northern California Robot Games

by @ 8:51 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

Western Region Robotics Forum
Saturday, October 13, 2007
Woodside High School New Gym
199 Churchill Avenue, oodside, CA 94062
Qualifying Matches 9:00 a.m.â?? 12:00 p.m., Playoffs 1:00 â??4:00 p.m.
More Info: http://www.e-grid.net/docs/0710-wrrf.pdf

The 2007 Northern California Robot Games is free and open to the public. It promises to be as fun and exciting for the spectators as it will be for the student participants. Cheering fans. Loud music. High School students (more…)

Mtg: Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators

by @ 8:47 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY October 15
SCV Circuits and Systems Chapter
Speaker: Ranjit Chandra, Gradient Design Automation
Time: Pizza/drinks at 6:30 PM, Presentation at 7:00 PM
Cost: no cost
Place: National Semicond — woops — Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas

Current IC design trends calls for integration of power transistors within high-performance mixed-signal designs. Because of the increased power densities caused by such trends, temperature variations within the chip need to be taken into account (more…)

September 12, 2007

Courses: Nanotech, Flipchip, Lead-free, IC Pkgng and Integration

by @ 12:57 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

IEEE Professional Development Courses
Full Day of Materials and IC/System Packaging Courses ? [more]
— October 3, 2007 ? ? — With the APM/IEMT Symposium (Oct. 4-5)
— Separate (non-symposium) registrations are encouraged
— Internationally-known experts coming to Silicon Valley? — held at San Jose Holiday Inn
— Member Registration: $300 for half-day, $450 for full day
— Four Morning PDCs:
Nanotechnology Applications in Packaging, Florin Ciontu, NanoSPRINT
Implementing Flip Chip and WLP Technology, Peter Elenius, E&G Technology Partners
Advanced Packaging Technology Solutions for Today’s Leading Edge Microelectronics, Charles B. Woychik, GE Global Research
Achieving High Reliability for Lead-Free Solder Joints – Materials Considerations, Dr. Ning-Cheng Lee, Indium Corp.
— Three Afternoon PDCs:
Polymers & Nano-Composites for Electronic and Photonic Packaging: Recent Advances in Materials and Processes, Prof. C.P. Wong, Georgia Institute of Technology
3-Dimensional Semiconductor Packaging & Integration, Charles E. Bauer, Ph.D., and Herbert J. Neuhaus, Ph.D., TechLead Corporation
Failure Modes & Analysis of Flip Chip Assemblies, Prof. Daniel Baldwin, Georgia Institute of Technology
See the Full Course Descriptions (PDF, 400 kB) and registration information, or our Chapter website: www.cpmt.org/scv.

Mtg: European Educational Programs and Internet Operations

by @ 12:54 pm. Filed under ALL, Communications, Engineering Mgmt, Optics/Displays
 

TUESDAY September 18
SF Communications Chapter
Speaker: Tim Ryan, Vice Chair and Network Manager, CCSF
Time: Complimentary pizza/salad/desert dinner at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: The California Public Utilities Commission, 505 Van Ness Ave, San Francisco; parking meters west of Van Ness are inactive after 6:00 PM
RSVP: by email to Michael Butler, mjbsf@verizon.net for a count

Mtg: The Missing System of Nanoscale Education

by @ 12:52 pm. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY September 18
SCV Nanotechnology Chapter
Speaker: Dr. Nora Sabelli, Senior Science Advisor, Center for Technology in Learning (CTL), SRI International
Time: Registration & light lunch 11:30 AM; Presentation at noon
Cost: Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1, CMA Room, 2900 Semiconductor Drive, Santa Clara
RSVP: on our website
Web: www.ieee.org/nano

The nanoscience revolution brings together diverse areas of human endeavor including science, medicine, industry, and environmental management. It requires a commensurate response in the educational community to increase students’ understanding of core concepts in the field. ? The presentation will discuss the results of a preliminary due-diligence study (more…)

Mtg: Joint Venture Risks

by @ 12:51 pm. Filed under ALL, Communications, Computers/Software, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

TUESDAY September 18
SCV Consultants’ Network of Silicon Valley
Speaker: Kevin Roe, Esq., Law Offices of Kevin Roe
Time: Presentation at 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

Many Bay Area companies and startups are at some point approached with attractive proposals for a joint venture. ? These typically come from foreign companies, and they frequently have disastrous results. This talk will cover the risks of joint ventures, (more…)

Mtg: State-of-the-art Ferrite Materials for Fundamental Research, Nano-science, and High-Frequency Applications

by @ 12:49 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY September 18
SCV Magnetics Chapter
Speaker: Prof. Vince Harris, Northeastern University, Boston
Time: Cookies and drinks at 7:30 PM; Presentation at 8:00 PM
Cost: none
Place: KOMAG, 1710 Automation Parkway, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/mag

Ferrite materials have long played an important role in power conditioning, conversion, and generation across a wide spectrum of frequencies (up to 10 decades). They remain the preferred magnetic materials, having suitably low losses, for most applications above 1 MHz, and are the only viable materials (more…)

Mtg: Transceiver Designs for Multicarrier Transmission

by @ 12:48 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY September 17
SCV Communications, with Circuits & Systems, Signal Processing? Chapter
Speaker: Distinguished Lecturer Prof. Yuan-Pei Lin, Department of Electrical and Control Engineering, National Chiao-Tung University, Taiwan
Time: Presentation at 6:00 PM
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.comsocscv.org

The multicarrier transceiver has found applications in a wide range of wired or wireless transmission channels.? It is typically called DMT (discrete multitone) for wired DSL (digital subscriber loops) applications such as ADSL (asymmetric DSL) and VDSL (very high-speed DSL), and called OFDM (orthogonal frequency division multiplexing) for wireless LAN (local area network) and broadcasting applications such as digital audio broadcasting (more…)

Mtg: Today’s Vacuum Electronics Industry: Powering Tomorrow’s Frontiers

by @ 12:46 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY September 13
SCV Microwave Theory and Techniques? Chapter
Speaker: Carter Armstrong, L-3 Communications Electron Devices
Time: Social at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Bldg #9 Classroom #4, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.mtt-scv.org

Energized by recent advances in 3D device modeling, long-life and high current density electron emitters, high power materials, precision fabrication, and amplifier integration and miniaturization, a new generation of RF vacuum electronics engineers is discovering the multidisciplinary attraction (more…)

Mtg: Nanotechnology, Molecules and the Future of Electronics

by @ 12:45 pm. Filed under ALL, BioEngineering, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

THURSDAY September 13
SCV Electron Devices Chapter
Speaker: Duncan Stewart, HP Labs
Time: Social at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

“Nanotechnology” will solve every materials, electronics and biology problem we have, according to some of the latest techno-hype.? Or destroy the world with self-replicating nano-robots, predicts popular fiction.? We will take a look at what is real, what is not real, (more…)

Mtg: Trends in State-of-the-Art Microscopy and Nanoscale Characterization

by @ 12:44 pm. Filed under ALL, Electronics Design, NanoEngineering, Optics/Displays, Semiconductors
 

WEDNESDAY September 12
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Edward Principe, Application Development Manager, Carl Zeiss SMT, Inc.
Time: Optional dinner at 6:30 PM, Presentation at 7:30 PM
Cost: Dinner $25 (by Sept. 10); no cost for meeting
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: by email to Janis Karklins, Karklins@ieee.org

Advances in analytical equipment and characterization techniques have gone hand-in-hand with advancements in electronics.? As we push the limits of technology so must we push the limits of characterization in order to verify or even understand what weâ??ve created, as well as to gain a deeper understanding of new phenomena.? Innovations in the science of microscopy and spectroscopy techniques (more…)

Mtg: Formation of a Warranty Chain Management Institute and its Applicability for Reliability Engineers

by @ 12:05 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY October 24
SCV Reliability Chapter
Speaker: Glen Griffiths and Allison Griffiths, Hewlett Packard
Time: Refreshments at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: HP-Cupertino Oak Room, Bldg 48, Pruneridge Ave. and Wolfe Rd., Cupertino
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/rl/events.htm

Warranty costs in the US alone run in the region of $28B per annum. Reliability Engineers have a significant influence on the failure rates of equipment, which is a key driver of warranty events and hence cost. Glen will outline the path he has taken, beginning with (more…)

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