IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

October 31, 2007

Annual SV Engineering Council’s Open House and optional Technology/Engineering Education Forum

by @ 5:56 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt, Semiconductors

TUESDAY November 13
Silicon Valley Engineering Council
Speakers: Elise Engelhardt, ASME, and others
Education Forum: 3:45pm – 5:30pm
Welcome Reception: 6:00pm-7:00pm
SVEC Presentations: 7:00pm-9:00pm
Welcoming Remarks and Acknowledgments: Elise Engelhardt, President, Silicon Valley Engineering Council
â?¢ Experience SVEC Educational Outreach Programs
– Discover “E” (Engineering)
– Tech Academy Summer Program
– Call for Nominations for Scholarships
â?¢ Announcement of 2008 Silicon Valley Engineering Hall of Fame Inductees
â?¢ Prepare for National Engineers Week 2008
Cost: none
Place: SEMI, 3081 Zanker Road, San Jose
RSVP: through EventBright,

Seminar: Vibro-Acoustics Simulation

by @ 8:40 am. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt

Vibro-Acoustics Simulation Seminar
– Thursday, December 13 ? ? – 10:00 AM – 2:30 PM
– Santa Clara Marriott ? ? – No cost; lunch will be provided
Based on AutoSEA2 (the industry standard for mid and high frequency noise and vibration analysis), VA One offers a unique and unprecedented combination of all standard vibro-acoustics simulation methods: Statistical Energy Analysis (SEA), Finite Element Analysis (FEA) and the Boundary Element Method (BEM). Discover why VA One is the ONE tool you need for full spectrum vibro-acoustic simulation.
Who Should Attend? ? – Current AutoSEA2 and SEA users and managers ? – Current BEM users and managers ? – Current FE acoustic software users and managers ? – Vibration, acoustics and dynamics engineers ? – Structural Analysts ? – CAE professionals
Applications: ? – Vibro-acoustics ? – Dynamic Environments ? – Random Vibration Analysis ? – Structure-borne Vibration ? – Pre-test Simulation ? – Mid-Frequency Analysis
Pre-registration is highly recommended. Visit
Download the Seminar flyer to register by FAX:

Int’l Symposium for Testing and Failure Analysis

by @ 8:39 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Optics/Displays, Semiconductors

33rd Int’l Symposium for Testing and Failure Analysis
– November 4-8, 2007 ? – San Jose Convention Center
ISTFA’07 combines technical sessions, tutorials, an exhibition, and user group meetings with a focus on making the full experience a strong benefit for the attendee.

  • 16 Technical Sessions & Panel Discussions
  • 4 Technology-Specific User Groups
  • 5 One-Day Pre- & Post-conference Short Courses
    Educational Tutorials:? – Materials Characterization for Failure Analysis ? – Failure Localization with Active and Passive Voltage Contrast in FIB and SEM ? – Failure Analysis Flow Decision Tree ? – The Role of the AFM in Yield and Failure Analysis ? – Reliability in MEMS Packaging ? – Analog Building Blocks: Circuits and Devices ? – Diagnosing Analog Circuits ? – Yield Basics for Failure Analysis including 300mm Water and Cu Technology (and more!) More information:
  • Conf: Printed Electronics USA 2007: Converging Printing with Electronics

    by @ 8:37 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

    Organic & printed inorganic electronics
    Printed Electronics USA 2007
    Converging Printing with Electronics: Commercializing the Technology
    – November 12-15, 2007 ? – South San Francisco Conference Center
    Aimed at product developers, end-users, researchers, scientists and venture capitalists, this event is the only one to cover all of organic and printed inorganic electronics.
    Over 65 presentations from leading global companies, including Kovio, Hasbro, Sony, Samsung, LG Philips, STMicroelectronics, T-Ink, PARC, Plastic ePrint. Full technological analysis is given on all areas of printed electronics including logic/memory, displays, power, sensors, materials, and manufacturing technologies.
    – Investment Summit ? – Exhibits ? – Special Tours ? – Masterclasses
    For more information & to register:

    One-day Seminar: New Frontiers in Computing Technology

    by @ 8:34 am. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt

    SATURDAY November 3
    SCV Computer Chapter
    Speakers: Eight academic and industry talks
    Cost: $50 for IEEE members, $55 non-members (through Oct. 29) — includes lunch, breaks
    Place: The Fremont Marriott, 46100 Landing Parkway, Fremont
    RSVP: register from the website

    Top speakers and experts from both Industry and the Research field:


    Richard M. Karp,? ? 1985 Turing Award Recipient. University of California Berkeley

    Lotfi Zadeh, IEEE Medal of Honor, 1995. University of California Berkeley

    Dieter Fensel,? University of Innsbruck

    Yoav Shoham,? Stanford University

    ? Anant Jhingran,? IBM Silicon Valley Laboratory, USA

    ? ? Enterprise Information Mashups: Integrating Information, Simply”

    Eric Brill,? Microsoft Research

    Andrew Tomkins,? Yahoo!

    Neel Sundaresan,? eBay Research Labs

    Mtg: Radar History Update – New and Illuminating Information on that “Bastard Invention”

    by @ 8:30 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt

    THURSDAY November 1
    Monterey Bay Subsection
    Speaker: Nicholas Willis
    Time: 3:00 PM
    Cost: none
    Place: Spanagel Hall Room 321, Naval Postgraduate School, Monterey
    RSVP: required, for access to the NPS campus; US citizens only; by email to D. Jenn,

    As usually happens during the ongoing development of a major invention, old information is released (or declassified) and new information surfaces.? Such is the case with radar, in particular the first radar, Christian Hulsmeyerâ??s 1904 telemobilskop, and then the â??re-discovery??? of radar in its bistatic configuration in the 1930s. (more…)

    Mtg: Educating Engineers in Advanced Silicon Processes

    by @ 8:28 am. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors

    WEDNESDAY December 19
    SCV Education Chapter
    Speaker: Dr. Kris Verma
    Time: dinner at 6:30 PM, Presentation at 7:00 PM
    Cost: none
    Place: Silicon Valley Technical Institute; 1762 Technology Dr., Suite 227, San Jose
    RSVP: not required


    During the last two decades, the Semiconductor Industry model? has changed from Vertical (Design, Fab, Test, and Packaging) under one IDM (Integrated Device Manufacturer) to a Horizontal model (Fabless Design Houses, IP developers, Wafer Mega Foundries, and subcontractors for test and assembly) under different companiesâ?? management. ? This new business model? (more…)

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