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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

December 30, 2007

Mtg: High Volume Print Forming: Filling the Gap between Nano and ‘Just-Plain-Miniature’ Devices

by @ 4:06 pm. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

WEDNESDAY February 13
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Arthur L. Chait, President, EoPlex Technologies
Time: Optional dinner at 6:30 PM, Presentation at 7:30 PM
Cost: $25 for dinner, no cost for presentation
Place: Ramada, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: by email with Janis Karklins, karklins@ieee.org
Web: www.cpmt.org/scv

? A great deal of progress has been made in the field of nano and related “tiny” technologies. ? Unfortunately, the technology to link the tiny world to the macro world has not kept pace. ? The space between nano and macro is immense. ? At the nano end are self-assembling structures and (more…)

Mtg: IC Chips – from Scaling to Emerging Nanotechnology

by @ 12:26 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY January 22
SCV Electron Devices Chapter
Speaker: Dr. Bin Yu, NASA Ames Research Center
Time: Refreshments at at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

 

It is predicted that silicon CMOS FET could be ultimately scaled down to 1.5 nm gate length based on the least energy model for computing. ? However, it is anticipated that a gate length of 4~5 nm would be the practical limit (more…)

Mtg: Silicon Technology Scaling and ESD Challenges

by @ 12:24 pm. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors
 

MONDAY January 14
SCV Electron Devices Chapter
Speaker: Dr. Charvaka Duvvury, Texas Instruments
Time: Refreshments at at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

 

The trends in silicon technology scaling towards the sub-100 nm range, along with the introduction of newer transistor structures such as the multi-gate and Fin-FET devices, are driving sensitive issues for ESD development and IC protection design.? This is compounded by the complex interactions (more…)

Mtg: ZigBee Wireless Sensors and Control Networks: A Watershed Event

by @ 11:28 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY February 19
SCV Consultants’ Network of Silicon Valley
Speaker: Bob Heile, ZigBee Alliance
Time: 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

 

Dr. Bob Heile is Chair of the ZigBee Alliance. ? This talk will provide an overview of the alliance and its mission. He will address (more…)

Mtg: An Overview of USB Device Implementation on Microcontrollers

by @ 11:21 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY January 15
SCV Consultants’ Network of Silicon Valley
Speakers: Tim Clark, Art Anderson, Cheri Keller, Microchip Technology, Inc.
Time: 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

 

The Universal Serial Bus (USB) is the industry standard for serial communications. It was originally intended as a replacement for the old-style serial and parallel connections on a PC, but its usefulness has broadened (more…)

Mtg: License-Free Wireless ISPs (WISPs) and the Challenges of FCC Part 15 Certification

by @ 11:07 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY January 8
SCV Electromagnetic Compatibility Chapter
Speaker: Jack Unger, Ask-Wi.Com, Inc. (formerly Wireless InfoNet, Inc.)
Time: Social at 5:30 PM, Presentation at 6:30 PM
Cost: none
Place: Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara
RSVP: not required
Web: www.scvemc.org

 

The FCC mandates that Part 15 license-free wireless equipment be tested and FCC certified, yet many wireless ISPs (WISPs) assemble at least some of their equipment in-house. ? Join us (more…)

Mtg: Ultrashort Pulsed Laser Applications in Biomedicine

by @ 10:52 am. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

WEDNESDAY January 16
SCV Engineering in Medicine and Biology Chapter
Speaker: Greg Spooner, Raydiance
Time: 7:30 PM
Cost: none
Place: Clark Center Auditorium, Stanford University (free parking after 4 PM)
RSVP: not required
Web: ieee.org/scv/embs

 

Lasers heat things up. ? Modifying materials with lasers frequently (though not always) involves a thermal interaction produced through linear absorption. ? High peak power and ultrashort pulsed lasers are different.? (more…)

December 20, 2007

Mtg: Design and Measurement of Coaxial-to-Planar Transitions to 110GHz and Beyond

by @ 9:41 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY January 10
SCV Microwave Theory and Techniques Chapter
Speaker: Ajaiey Sharma, Anritsu
Time: Refreshments at at 6:00 PM, Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building 9, Classroom 4, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.mtt-scv.org

 

The transition from coax to a planar circuit is often one of the more difficult areas to both design and to manufacture. ? The coax involved is typically the back-end of a connector, but can also be a coaxial cable.? (more…)

December 18, 2007

Tour: the FPL Greenridge Windfarm in Livermore

by @ 2:46 pm. Filed under ALL, Electrical/Power, Engineering Mgmt
 

WEDNESDAY January 16
OEB Power Engineering Chapter
Organizer: Diep Nguyen, P.E., DTN Engineers, Inc. 510 267-0441, Diep@ieee.org
Time: 4:00 PM
Cost: none
Place: Florida Power and Light Energy Group 6185 Industrial Way, Livermore
RSVP: required due to site access and security; by email to Carole Pharr, Carole.Pharr@Salaobrien.com, 408-282-1500
Web: www.e-grid.net/docs/0801-oeb-pes.pdf

 

The event will be started with the short tour of the Florida Power and Light (FPL) Energy Group Operations and Maintenance building before going out to the site to see the windmills up close. ? (more…)

Mtg: An Open Baseband Processing Architecture for Future Mobile Terminal Design

by @ 2:19 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY January 7
SCV Signal Processing Chapter
Speaker: Prof. Willie W. Lu, U.S. Center for Wireless Communications
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: $2 toward refreshments
Place: National Semiconductor (north end of Building E), Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/sps

The future wireless and mobile communications will be shifted from the traditional transmission-specific technology to the interface-specific technology to be able to converge with the computer system architecture. The OWA technology offers an optimal solution to open up the wireless platform (more…)

Mtg: Panel Discussion – Best of ISTFA

by @ 2:09 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY January 23
SCV Reliability Chapter
Organizer: Art Rawers
Time: Refreshments at 6:30 PM, Presentation at 7:00 PM,
Cost: none
Place: Hewlett Packard Oak Room, Bldg 48 (Just North of Hwy 280, Wolfe Rd Exit), Cupertino
RSVP: not required, but email reliability@ieee.org if you are interested in being on the panel or contributing
Web: www.ewh.ieee.org/r6/scv/rl

 

The International Symposium for Testing and Failure Analysis (ISTFA) provides a forum for the latest developments in wafer, chip, package, and board level test and failure analysis. The 30th ISTFA was held (more…)

December 7, 2007

Mtg: Educating Engineers in Advanced Silicon Processes

by @ 6:38 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY December 19
SCV Education Chapter
Speaker: Dr. Kris Verma
Time: dinner at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Silicon Valley Technical Institute; 1762 Technology Dr., Suite 227, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/es

 

During the last two decades, the Semiconductor Industry model? has changed from Vertical (Design, Fab, Test, and Packaging) under one IDM (Integrated Device Manufacturer) to a Horizontal model (Fabless Design Houses, IP developers, Wafer Mega Foundries, and subcontractors for test and assembly) under different companiesâ?? management. ? This new business model? (more…)

Mtg: Small Stuff in Search of the Big Bucks: Nanotechnology Commercialization by Sector

by @ 6:37 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

TUESDAY December 18
SCV Nanotechnology Chapter
Speaker: Kristin Abkemeier, Ph.D., Analyst at Lux Research, Inc.
Time: Registration & Light Lunch 11:30 AM, Presentation at Noon
Cost: IEEE Members and Students $5. Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: at the website
Web: www.ieee.org/nano

Nanotechnology is shifting from research labs to markets, as world investments reached $12.6 billion in 2006. ? With the first applications in-market in the materials, electronics and energy, and life science sectors, the impact of nanotechnology in different industries varies from broad and incremental in nature, (more…)

Mtg: Nanowires and Nanolasers: How Small can a Laser be?

by @ 6:36 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

THURSDAY December 13
SCV Lasers and Electro Optics Chapter
Speaker: Prof. Cun-Zheng Ning, Arizona State University, and LEOS Distinguished Lecturer
Time: Networking and Food: 7:00 PM, Presentation: 8:00 PM
Cost: none
Place: National Semiconductor Building E Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: by email to ieeescvleos-rsvp2007@yahoo.com
Web:
www.ewh.ieee.org/r6/scv/leos

 

The pursuit of nanotechnology in general and miniaturization of electronic devices in particular have seriously challenged the optoelectronics community to develop ever smaller lasers and optoelectronic devices compatible with the trend in microelectronics. Vertical-cavity surface emitting lasers measured a few microns were once the smallest lasers. ? The situation is now rapidly changing over the last 5 years with the demonstration of lasing capability of a single semiconductor nanowire of ~ 100 nanometers in diameter. ? The ultimate challenge to the community is: can one make a laser that is smaller than the wavelength in all 3 dimensions, or what is the ultimate size limit of a laser?

To answer this and related questions, my lecture will start with an overview of impressive recent progress in growth, fabrication, and characterization of semiconductor nanowires and demonstration of lasing activities in various wavelengths. ? These lasers represent one of the smallest lasers of any kind (more…)

Mtg: PLL Design Essentials for Wireless Systems

by @ 6:35 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY December 13
SCV Microwave Theory and Techniques Chapter
Speaker: Derek K. Shaeffer, RF Engineering Manager, Beceem Communications
Time: Refreshment and Social Hour at 6:00 PM, Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Bldg #9, Classroom #4, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.mtt-scv.org

 

This talk provides an overview of PLL design fundamentals and reviews performance considerations that typify wireless systems.? By the end of the talk, attendees will understand how to translate system performance requirements into synthesizer design specifications (more…)

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