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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

December 7, 2007

Mtg: Electrical Out-of-Step Protection

by @ 6:34 pm. Filed under ALL, Electrical/Power, Engineering Mgmt
 

THURSDAY December 13
SF Power Engineering Chapter
Speaker: Demetrios Tziouvaras, Schweitzer Engineering Laboratories, Inc.
Time: Noon (includes lunch)
Cost: free for IEEE members; $5 for non-members
Place: Pacific Gas & Electric Office, 245 Market St., Conference Room 1411, San Francisco
RSVP: by Dec. 6th (first 25 people only) to Davis Erwin, dpe4@pge.com, 415-973-6010
Web: www.e-grid.net/docs/0712-sf-pes.pdf

 

Alternating current (AC) electrical networks can experience loss of synchronism (out-of-step, OOS) during stressed power system conditions. ? During an OOS event, large current and voltage excursions develop across the electrical connection between two diverging grid sections.? (more…)

Mtg: Technical Management in Silicon Valley

by @ 6:33 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt
 

THURSDAY December 13
SCV Engineering Management Chapter
Subject: Technical Management in Silicon Valley (Topical discussions; election of officers)
Time: 7:30 AM (no-host breakfast)
Cost: no cost
Place: DENNY’S, 311 S. Mathilda Avenue, Sunnyvale
RSVP: not needed
Web: www.ieee-scv-ems.org

? Our objective, during this informal breakfast, is to network on technical management vs. leadership รข?? where this discipline is going and what is available education-wise; have a discussion about what topics members would like for future local meetings;? (more…)

Mtg: Radiated and Conducted Emission Debug Techniques

by @ 6:32 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY December 11
SCV Electromagnetic Compatibility, and Product Safety Engineering Chapters
Speaker: Dr. Keith Hardin, Lexmark International, Inc.
Time: catered ‘Holiday Celebration’ dinner at 5:30 PM; elections; presentation at 6:30 PM
Cost: none
Place: Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara
RSVP: not required
Web: www.scvemc.org

Radiated and conducted emissions contain spectral and time domain information that can be very helpful in determining the sources of the emissions and possible countermeasures for information technology products. This presentation will discuss a number of methods (more…)

Mtg: Wireless Standards: A History and Perspective / CNSV Annual Meeting

by @ 6:29 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY December 11
SCV Consultants’ Network of Silicon Valley
Speaker: Bruce Himebauch, Atheros Communications
Time: Election of Officers at 7:00 PM; presentation at 7:15 PM
Cost: none
Place: Silicon Valley Technical Institute, 1762 Technology Dr., Suite 227, San Jose
RSVP: not required
Web: www.CaliforniaConsultants.org

Most commercial wireless networking products conform to the 802.11b, 802.11a, 802.11g and 802.11n standards, collectively known as Wireless Fidelity (Wi-Fi). Wi-Fi has been accepted in businesses, schools, government and homes as an alternative to wired LANs. ? The 802,11 standards have similarities (more…)

Mtg: Nanotechnology Trends in Nonvolatile Memory Devices

by @ 6:28 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY January 15
SCV Nanotechnology Chapter
Speaker: Gian-Luca Bona, Ph.D., Dept Group Manager of Science & Technology, IBM Almaden Research Center
Time: Light lunch 11:30 AM, Presentation at Noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

A large variety of materials for applications in non-volatile storage memories is currently being explored in academic research and industrial development laboratories. ? The technologies considered range from magnetic domain switching to resistance switching in phase change chalcogenide materials, solid electrolytes as well as (more…)

December 5, 2007

Mtg: A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects

by @ 5:19 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

THURSDAY January 17
SCV Solid State Circuits Chapter
Speaker: Samuel Palermo, Intel
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: donation for food
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

? As I/O bit rates have increased in order to accommodate growing on-chip aggregate bandwidth in high-performance systems, the disparity between optical and electrical channels at the board and box level is magnified.? This increases electrical link equalization complexity and leads system designers to consider optical interconnects (more…)

December 4, 2007

Mtg:Re-Live the Movie “The Matrix”: From Harry Nyquist to Image-Based Rendering

by @ 6:12 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY December 10
SCV Signal Processing Chapter
Speaker: Prof. Tsuhan Chen, Department of Electrical and Computer Engineering, Carnegie Mellon University, and IEEE Distinguished Lecturer
Time: Fast Food & drinks at 6:30 PM; Presentation at 7:00 PM
Cost: $2 Donation Recommended towards Refreshments
Place: National Semiconductor (north end of Building E), 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/sps

In recent years, the field of visual computing has observed a convergence of image processing, computer vision, and computer graphics. Multiview imaging represents one central theme of the convergence. Now widely used in applications ranging from special effects (e.g., in the movie “The Matrix”) to 3D object tracking, multiview imaging has become an essential tool (more…)

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