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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

December 18, 2007

Tour: the FPL Greenridge Windfarm in Livermore

by @ 2:46 pm. Filed under ALL, Electrical/Power, Engineering Mgmt
 

WEDNESDAY January 16
OEB Power Engineering Chapter
Organizer: Diep Nguyen, P.E., DTN Engineers, Inc. 510 267-0441, Diep@ieee.org
Time: 4:00 PM
Cost: none
Place: Florida Power and Light Energy Group 6185 Industrial Way, Livermore
RSVP: required due to site access and security; by email to Carole Pharr, Carole.Pharr@Salaobrien.com, 408-282-1500
Web: www.e-grid.net/docs/0801-oeb-pes.pdf

 

The event will be started with the short tour of the Florida Power and Light (FPL) Energy Group Operations and Maintenance building before going out to the site to see the windmills up close. ? (more…)

Mtg: An Open Baseband Processing Architecture for Future Mobile Terminal Design

by @ 2:19 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY January 7
SCV Signal Processing Chapter
Speaker: Prof. Willie W. Lu, U.S. Center for Wireless Communications
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: $2 toward refreshments
Place: National Semiconductor (north end of Building E), Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/sps

The future wireless and mobile communications will be shifted from the traditional transmission-specific technology to the interface-specific technology to be able to converge with the computer system architecture. The OWA technology offers an optimal solution to open up the wireless platform (more…)

Mtg: Panel Discussion – Best of ISTFA

by @ 2:09 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY January 23
SCV Reliability Chapter
Organizer: Art Rawers
Time: Refreshments at 6:30 PM, Presentation at 7:00 PM,
Cost: none
Place: Hewlett Packard Oak Room, Bldg 48 (Just North of Hwy 280, Wolfe Rd Exit), Cupertino
RSVP: not required, but email reliability@ieee.org if you are interested in being on the panel or contributing
Web: www.ewh.ieee.org/r6/scv/rl

 

The International Symposium for Testing and Failure Analysis (ISTFA) provides a forum for the latest developments in wafer, chip, package, and board level test and failure analysis. The 30th ISTFA was held (more…)

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