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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

January 30, 2008

Mtg: Unique Testing For Products Containing TNV Circuits

by @ 5:25 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY February 26
SCV Product Safety Engineering Chapter
Speaker: Peter Tarver, Sanmina-SCI Corporation
Time: Optional dinner: 5:45 PM at El Torito; Presentation at 7:00 PM at Bowers Cafe
Cost: $5 for IEEE members, $10 for non-members
Place: Socialize at El Torito Mexican Restaurant, 2950 Lakeside Drive, Santa Clara; talk is at Applied Materials, Bowers Café, 3090 Bowers Ave, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/pses

Does your equipment EVER connect to a Telecommunication Network? You think so? Youâ??re not sure?? Find out what NRTLs will expect you to do! Tonightâ??s â??advanced??? topic on TNV circuits (more…)

Mtg: Atomic Scale Modeling of Electron Transport in MRAM

by @ 12:28 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY March 18
SCV Nanotechnology Chapter
Speaker: Dr. Dimitri Novikov, CTO, Atomistix, Inc.
Time: Registration & light lunch 11:30 AM, Presentation at Noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor, Bldg E-1 CMA Room, 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

Atomic-scale modeling is becoming an important step in the process of designing novel advanced electronic devices, especially at the nanoscale size. Modeling R&D efforts are growing much faster than experimental research. ? One of the most prominent areas (more…)

Mtg: Holistic Transmission and Resource Planning

by @ 11:43 am. Filed under ALL, Electrical/Power, Engineering Mgmt
 

MONDAY March 3
SF Power Engineering Chapter
Speaker: Stephen T. Lee, senior technical executive, Electric Power Research Institute
Time: Noon
Cost: none for IEEE members, $5 for non-members (includes lunch)
Place: CPUC Building, Courtyard Training Room, 505 Van Ness Ave., San Francisco
RSVP: required by Feb. 29th, by phone or email to Chuck Magee, pesnews@yahoo.com, 415-703-4683 (for lunch count)
Web: www.e-grid.net/docs/0803-sf-pes.pdf

Holistic planning is a new concept that recognizes the reality of today’s fragmented organizational structures of the power industry and is a philosophy and methodology that attempts to reap the benefits of optimal resource allocation without reverting to a fully integrated and highly regulated environment. ? (more…)

January 27, 2008

SCU Grad Engng: Open House – Learn about Graduate Courses & Programs

by @ 8:22 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

Santa Clara University Graduate School of Engineering:
Open House – Learn about Graduate Courses & Programs
FIND OUT MORE! Come to one of these Information Sessions:
February 12 (Tues), 5:15 PM or March 11 (Tues), 5:15 PM
www.scu.edu/engineering/graduate

SCU’s School of Engineering offers masters and Ph.D. degrees, professional certificates, and Open University programs in Applied Mathematics, Computer, Electrical, Mechanical, Software Engineering, and Engineering Management. (more…)

Silicon Valley Engineers Week Banquet

by @ 8:19 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

Silicon Valley Engineering Council (SVEC)
Silicon Valley Engineers Week Banquet
— February 28, 2008 ? ? — Doubletree Hilton Hotel, San Jose
— Regular parking is validated ? ? — Reception 5:30 PM; Dinner 6:30 PM
Earlybird pricing through Feb 8th; more information at www.svec.org
We are seeking corporate and organizational sponsors for our scholarships!

Hall of Fame inductees will include Dr. Ernest Kuh (Engineering Dean Emeritus, UC-Berkeley), Stanley T. Myers (President & CEO, SEMI), W.J. “Jerry” Sanders III (Founder, Advanced Micro Devices). (more…)

Course: Design and Test with Verilog and SystemC

by @ 8:18 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

Worcester Polytechnic Institute
Design and Test with Verilog and SystemC?
— 10-week courses delivered online — Spring course starts in March
— 3 Units of Graduate-level instruction
For the full course outline, visit our website: cpe.wpi.edu/Corporate/advanc773.html.
Weekly lectures and discussion sessions: Two 45-minute weekly online lectures can be viewed at any time during the week of the lecture. Homework and exams are online. Each course starts with (more…)

Mtg: Ultra-thin Chips – a New Paradigm in Silicon Technology

by @ 6:08 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

FRIDAY February 8
SCV Electron Devices Chapter
Speaker: Dr. Joachim N. Burghartz, Institute for Microelectronics Stuttgart (IMS CHIPS)
Time: 5:15 PM (Social), 5:30 PM (Presentation)
Cost: none
Place: National Semiconductor Corp. Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

In contrast to conventional thick silicon chips, ultra-thin chips will be the basis for new applications, such as 3D integrated circuits (3D-ICs) and plastic electronics. ? This talk will introduce and compare two generically different process technologies (more…)

January 25, 2008

Mtg: Flip-Chip Substrates For Advanced Applications

by @ 2:58 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

THURSDAY March 27
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Bernd Appelt, Director, Worldwide Business Development, ASE (U.S.) Inc.
Time: Lunch at 11:45 AM, Presentation at Noon
Cost: $15 if reserved by March 24; $20 at door
Place: Ramada, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: by email with Ed Aoki, aoki.ed@gmail.com
Web: www.cpmt.org/scv

The continuing advancements in silicon technology are driving further innovation in flip-chip substrate technology. Market dynamics have lead to a de facto standardization of build-up technology for flip chip substrates for CPUs, graphics and gaming processors (more…)

Mtg: Power System Harmonics Mitigation for IT, Industrial and Commercial Facilities

by @ 2:43 pm. Filed under ALL, Electrical/Power, Engineering Mgmt
 

WEDNESDAY February 20
SCV Power Engineering & Industry Applications Chapter
Speaker: Ben Banerjee, Power Quality Sales Application Engineer, Square D Company
Time: Dinner 6:00 PM, Presentation 6:45 PM
Cost: $25.00 IEEE members, $30.00 nonmembers, $10.00 students
Place: Ramada Inn, 1217 Wildwood, Sunnyvale
RSVP: to James Alvers, james.alvers@us.schneider-electric.com, 925-463-7115
Web: www.e-grid.net/docs/0802-scv-pes.pdf

? Harmonic load is a major source of stress and inefficiency in an electrical system. It causes damage, downtime and expense. Typical power distribution systems at IT, industrial and commercial facilities include a large variety (more…)

Mtg: What Makes Engineering Managers Succeed?

by @ 8:51 am. Filed under ALL, Communications, Computers/Software, Engineering Mgmt
 

WEDNESDAY January 30
SCV Technical Management Chapter
Speaker: Chris Sims, Founder, Technical Management Institute
Time: Directed Networking â?? 6:30 PM; Dinner at 7:00 PM; Presentation at 7:45 PM
Cost: $25 for IEEE member, $30 for non member ($5 more if not preregistered)
Place: Ramada, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: on website
Web: www.ieee-scv-ems.org

Have you worked for a great manager? What were the qualities that made him or her stand out from the rest? What are the most important qualities or skills for an engineering manager to posses? Come share (more…)

Mtg: The Spin on Electronics! Spin-valves and Magnetic Tunneling Junctions

by @ 8:50 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY January 29
SCV Magnetics Chapter
Speaker: Stuart Parkin, IBM Almaden Research Center, and 2008 IEEE Magnetics Society Distinguished Lecturer
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Cost: none
Place: WDC (formerly Komag), 1710 Automation Parkway, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/mag

Today, nearly all microelectronic devices are based on storing or flowing the electronâ??s charge. ? The electron also possesses a quantum mechanical property termed “spin”, that gives rise to magnetism. Electrical current is comprised of (more…)

Mtg: Fourth Generation (4G) Mobile Smartphone Architecture Targeted for China and US Markets

by @ 8:09 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY April 9
SCV Communications Chapter
Speaker: Prof. Willie W. Lu, U.S. Center for Wireless Communications (USCWC)
Time: 6:00 PM
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/comsoc

The future wireless and mobile communications terminal device will be shifted from the traditional transmission-specific technology to an interface-based technology to be able to converge with the computer system architecture. This talk will present an open architecture platform (more…)

Mtg: Telepresence – giving the feeling of being in another location

by @ 7:56 am. Filed under ALL, Communications, Engineering Mgmt, Optics/Displays
 

WEDNESDAY February 13
SCV Communications Chapter
Speaker: Chuck Stucki, Vice President/General Manager, TelePresence Systems Business Unit, Cisco
Time: 6:00 PM
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/comsoc

 

Today’s collaboration tools significantly boost productivity â?? however, most users would agree that they are still no substitute for being there “in person.” Early videoconferencing solutions tried to emulate the face-to-face meeting experience, but it’s difficult to find a business executive (more…)

January 24, 2008

Mtg: Using a Spatial View to Understand and Solve Common Power Bypass Problems

by @ 8:26 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY February 12
SCV Electromagnetic Compatibility Chapter
Speaker: Steve Weir, Teraspeed Consulting Group LLC
Time: Social at 5:30 PM, Presentation at 6:30 PM
Cost: none
Place: Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara
RSVP: not required
Web: www.scvemc.org

? An ideal power delivery system exhibits a flat impedance at a low enough value across the load frequency. ? In practice this is not practical: as ICs routinely depend on a specific minimum real power supply impedance, (more…)

Mtg: Best of the RAMS Conference (held in Las Vegas in January)

by @ 8:14 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY February 27
SCV Reliability Chapter
Speakers: highlights and conclusions from Chapter attendees at RAMS
Time: Refreshments at 6:30 PM; Panel/Discussions at 7:00 PM
Cost: none
Place: HP-Cupertino Oak Room, Bldg 48 (corner of Pruneridge Ave. and Wolfe Rd.), Cupertino
RSVP: not required, but to be on the panel, email to reliability@ieee.org
Web: www.ewh.ieee.org/r6/scv/rl

The 54th annual Reliability and Maintainability Symposium (RAMS) was held in Las Vegas on January 28-31, 2008. ? For those of you who couldn’t attend, we will bring the Symposium to you (except for the slot machines). ? This evening offers highlights (more…)

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