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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

January 24, 2008

Mtg: New Horizons for Breast Radiotherapy

by @ 5:22 pm. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt, Optics/Displays
 

TUESDAY February 19
SF Engineering in Medicine and Biology Chapter
Speaker: Catherine Park, M.D., UCSF Department of Radiation Oncology
Time: No-host bar at 6:00 PM, Dinner at 7:00 PM, Presentation at 7:30 PM
Cost: $10 students, $15 members, $25 non-members
Place: Sinbadâ??s Restaurant, Pier 2 Embarcadero St., San Francisco
RSVP: by Feb 15th to Bob Giebeler, b.giebeler@ieee.org, 415-252-7214
Web: www.e-grid.net/docs/0802-sf-emb.pdf

? ? Our presenter Catherine Park, M.D. joined the faculty of the UCSF Department of Radiation Oncology in 2000 where she has pursued an interest in breast cancer research and treatment.? Her research interests include developing novel imaging and biologic targets to individualize treatment for patients (more…)

Mtg: Area- and Energy-Efficient VLSI Architectures for Low-Density Parity-Check Decoders

by @ 4:40 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY February 21
SCV Solid State Circuits Chapter
Speaker: Kiran Gunnam, LSI Corporation
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor Building E, Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

 

This talk presents several efficient decoder architectures for advanced error correction systems using low-density parity-check (LDPC) codes. ? Several structured properties of LDPC codes and decoding algorithms are observed and are used (more…)

January 21, 2008

Mtg: Emerging Display Trends in the Notebook PC Market

by @ 9:01 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

TUESDAY February 26 (Talk Title, Discription updated: 2/7/2008)
SCV Consumer Electronics Chapter
Speaker: John Jacobs, Director of Notebook Market Research, DisplaySearch
Time: Pizza + Drinks at 6:30 PM; Talk and Questions at 7:00 PM
Cost: $5 for IEEE members, $10 for non-members
Place: Oak Room at H-P, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: not required
Web: www.ieee.org/scvce

? John Jacobs ill discuss current trends in notebook displays, paying particular attention to the dominant trends in display size, aspect ratio and resolution. Additionally, technology such as LED backlighting, the influence of panel manufacturing efficiencies (more…)

January 19, 2008

Mtg: Panel Discussion – Best of ISTFA

by @ 5:11 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY January 23
SCV Reliability
Subject:
Organizer: Art Rawers
Time: Refreshments at 6:30 PM, Presentation at 7:00 PM,
Cost: none
Place: Hewlett Packard Oak Room, Bldg 48 (Just North of Hwy 280, Wolfe Rd Exit), Cupertino
RSVP: not required, but email reliability@ieee.org if you are interested in being on the panel or contributing
Web: www.ewh.ieee.org/r6/scv/rl?

The International Symposium for Testing and Failure Analysis (ISTFA) provides a forum for the latest developments in wafer, chip, package, and board level test and failure analysis. ? The 30th ISTFA was held November 4-8, 2007, in San Jose. (more…)

Mtg: Medical Device Regulations – from Design to Certification

by @ 5:10 pm. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt
 

TUESDAY January 22
SCV Product Safety Engineering Chapter
Speaker: Frank Eng, Food & Drug Administration
Time: Optional dinner at El Torito at 5:45 PM; Presentation (no charge) at Bowers Cafe at 7:00 PM
Cost: none for presentation
Place: Dinner at El Torito Mexican Restaurant, 2950 Lakeside Drive, Santa Clara; Presentation at Applied Materials, Bowers Café, 3090 Bowers Ave, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/pses

FDA and CDRH reports are just the culmination of a long sequence of events, so this presentation is intended both for regulatory personnel and for device development engineers. Engineers design and develop products that are as safe and effective (more…)

Mtg: IC Chips – from Scaling to Emerging Nanotechnology

by @ 5:06 pm. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY January 22
SCV Electron Devices? Chapter
Speaker: Dr. Bin Yu, NASA Ames Research Center
Time: Refreshments at at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

It is predicted that silicon CMOS FET could be ultimately scaled down to 1.5 nm gate length based on the least energy model for computing. ? However, it is anticipated that a gate length of 4~5 nm would be the practical limit (more…)

Mtg: Secondary Unit Substation Transformers

by @ 5:05 pm. Filed under ALL, Electrical/Power, Engineering Mgmt
 

TUESDAY January 22
SF Industry Applications Chapter
Speaker: Daniel Bumblauskas, ABB Inc.
Time: Social at 5:30 PM, Presentation at 6:00 PM, Dinner at 7:00 PM
Cost: $20 for dinner
Place: Sinbadâ??s Restaurant, Pier 2 The Embarcadero, San Francisco
RSVP: by email to Jack Lin, jlin@sfwater.org to reserve and be entered in drawing
Web: www.e-grid.net/docs/0801-sf-ias.pdf

Our speaker will discuss the application of liquid and dry-type secondary unit substation transformers. He will compare the advantages and disadvantages (more…)

Mtg: Variation Robustness for Analog/Mixed-Signal, Custom Digital, and Memory Design

by @ 5:00 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY January 21
SCV Circuits and Systems Chapter
Speaker: Patrick Drennan, Chief Technology Officer, Solido Design Automation, Inc.
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

As process technologies and supply voltages shrink, designers are faced with a pressing need to address systematic and random sources of variation in a more deliberate and thorough way. ? Accounting for variation within the flow of design has not progressed (more…)

Mtg: Consumer Electronics Show (CES) Report

by @ 4:56 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

TUESDAY January 22
SCV Consumer Electronics Chapter
Speakers: Five Chapter attendees
Time: Pizza + Drinks at 6:30 PM; Talk and Questions at 7:00 PM
Cost: $5 for IEEE members, $10 for non-members
Place: Oak Room at H-P, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: not required
Web: www.ieee.org/scvce

Five members of IEEE Consumer Electronics Society will share their photos and insights on a variety of topics that they covered at the 2008 Consumer Electronics Show and the International Conference on Consumer Electronics (ICCE).? Some of the photos (more…)

January 17, 2008

Mtg: Nonlinear Network Analysis

by @ 12:01 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY March 13
SCV Microwave Theory and Techniques Chapter
Speaker: Loren Betts, Agilent Technologies
Time: Refreshments at 6:00 PM, Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building 9, Classroom 4, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.mtt-scv.org

 

Recent advances in VNA HW and measurement algorithms provide the means to accurately measure and model the RF and Microwave nonlinear characteristics of devices. ? This presentation will discuss the error correction algorithms used to accurately measure nonlinear device characteristics, (more…)

Mtg: Vector Network Analyzer Extensions

by @ 11:51 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY February 14
SCV Microwave Theory and Techniques Chapter
Speaker: David V. Blackham, Agilent
Time: Refreshments at 6:00 PM, Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building 9, Classroom 4, 2900 Semiconductor Dr, Santa Clara
RSVP: not required
Web: www.mtt-scv.org

 

Recent enhancements to vector network analyzers (VNA) enable a broader range of measurements. ? This presentation will review fundamental concepts of vector error correction and how these concepts are extended (more…)

January 16, 2008

Mtg: Using Thermal Analysis as a Tool to Aid Analog Floorplanning

by @ 11:11 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY March 17 (postponed from February 18)
SCV Circuits and Systems Chapter
Speaker: David Schwan, CAD and Layout Manager, RFMD
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

Todays’ IC designers are being driven to reduce area and increase performance and power-efficiency. Local circuit temperature can affect circuit performance, speed and current consumption, as well create reliability problems like electro-migration and thermal-runaway. Temperature can be an engineered parameter, (more…)

January 15, 2008

Mtg: What Makes Engineering Managers Succeed? (plus Directed Networking)

by @ 9:23 am. Filed under ALL, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY January 30
SCV Technical Management Chapter
Speaker: Chris Sims, Founder, Technical Management Institute
Time: Directed Networking â?? 6:30 PM (with Carl Angotti, facilitator); Dinner at 7:00 PM; Presentation at 7:45 PM
Cost: $25 for IEEE member, $30 for non member ($5 more if not preregistered)
Place: Ramada, 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: on website
Web: www.ieee-scv-ems.org

Have you worked for a great manager? What were the qualities that made him or her stand out from the rest? What are the most important qualities or skills for an engineering manager to posses? Come share your experience and tap into the collective wisdom (more…)

January 13, 2008

Mtg: Performance Limitations of Cu/low-k Interconnects and Possible Alternatives

by @ 6:50 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY February 19
SCV Nanotechnology Chapter
Speaker: Prof. Krishna Saraswat, Stanford University, Department of Electrical Engineering
Time: Registration & light lunch 11:30 AM, Presentation at noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: through the website
Web: www.ieee.org/nano

 

For more than 30 years, the performance of silicon integrated circuits has improved at an astonishing rate. ? However, looking into the future the relentless scaling paradigm is threatened by fundamental limits including excessive power dissipation, insufficient communication bandwidth, (more…)

Mtg: Nanomaterials for Alternative Energy: Battery Pack Systems

by @ 11:20 am. Filed under ALL, Electrical/Power, Engineering Mgmt, NanoEngineering
 

TUESDAY February 19
OEB Power Engineering Chapter
Speaker: Bob Goebel, Vice President Sales and Marketing, Altair Nanotechnologies
Time: 6:30 PM
Cost: $15 for members and students, $25 for non-members
Place: Scotts Seafood in Jack London Square, Oakland
RSVP: by email to Carole Pharr, wpharr@aol.com
Web: www.e-grid.net/docs/0802-oeb-pes.pdf

 

Altairnano is a leading manufacturer of advanced battery pack systems, which are used in stationary power applications, and electric and hybrid-electric vehicles. They have substantial experience in commercializing innovative, disruptive technologies. (more…)

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