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January 16, 2008

Mtg: Using Thermal Analysis as a Tool to Aid Analog Floorplanning

by @ 11:11 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY March 17 (postponed from February 18)
SCV Circuits and Systems Chapter
Speaker: David Schwan, CAD and Layout Manager, RFMD
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

Todays’ IC designers are being driven to reduce area and increase performance and power-efficiency. Local circuit temperature can affect circuit performance, speed and current consumption, as well create reliability problems like electro-migration and thermal-runaway. Temperature can be an engineered parameter, (more…)

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