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March 12, 2008

Mtg: The Promise of Kigh-k/metal Gates – From Electronic Transport Phenomena to Emerging Device/circuit Applications

by @ 7:21 am. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors
 

TUESDAY March 18
SCV Electron Devices Chapter
Speaker: Dr. Kingsuk Maitra, AMD
Time: 6:00 PM – Pizza, 6:15 PM – Lecture
Cost: none
Place: National Semiconductor, Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backdrop, the inter-action of high-k/metal gates with end of roadmap devices would be thoroughly explored.
High-k/metal gates have interesting ramifications in the circuit space-from NBTI (negative bias temperature instability) to high-field mobility, the high-k gate induced physical phenomena and their impact on device and circuit performance and reliability would be discussed.
To conclude, this talk would also conjecture on the continued scalability of highk gate stacks for futuristic CMOS device architectures.

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