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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 14, 2008

Mtg: Reliable Wireless Sensor Networks

by @ 3:26 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors

OEB Industry Applications Chapter
Speaker: Kurt Ottaway, Senior Field Application Engineer, Dust Networks
Time: No-host social at 5:30 PM; Presentation at 6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM
Cost: Dinner is $20 for IEEE members; $25 for non-members
Place: Marie Callender’s Restaurant – The Garden Room; 2090 Diamond Blvd in Concord (near the Concord Hilton Hotel)
RSVP: by email to Gregg Boltz, – 925-210-2571

In todayâ??s demanding and competitive business environment, the need to collect, interpret and act on real-time data plays an increasingly vital role.? But data collection using typical wired sensor networks has always been expensive (more…)

Mtg: 1.8 Gpulses/s UWB Transmitter in 90nm CMOS

by @ 3:24 pm. Filed under ALL, Communications, Electronics Design, Semiconductors

SCV Solid State Circuits Chapter
Speaker: Murat Demirkan, University of California, Davis
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor Building E, Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required


This presentation is based on the speakerâ??s Ph.D. dissertation which focuses on the design of a pulse-based ultra-wideband (UWB) transmitter. The transmitter consists of a pulse generator, a phase-locked loop (PLL) and modulation circuitry. ? The novel pulse generator (more…)

Mtg: Robotically Assisted Surgery: How daVinci Works Now and How It Could Evolve

by @ 3:23 pm. Filed under ALL, BioEngineering, Electronics Design, Optics/Displays, Semiconductors

SCV Engineering in Medicine and Biology Chapter
Speaker: William C. Nowlin, Ph.D, Intuitive Surgical
Time: No-host dinner at 6:15 PM, Presentation at 7:30 PM
Cost: none, for presentation
Place: Optional Dinner, Stanford Hospital Cafeteria, 6:15 PM (no reservations); talk at Clark Center Auditorium, Stanford Univ.
RSVP: not required


Intuitive Surgical makes the daVinciâ?¢ Surgical System, which is variously described as a “robot”, a “telesurgical system”, and a “mechanism for minimally invasive surgery”. ? In this presentation, I’ll give a general introduction (more…)

Mtg: The Promise of Kigh-k/metal Gates – From Electronic Transport Phenomena to Emerging Device/Circuit Applications

by @ 3:22 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors

TUESDAY March 18
SCV Electron Devices Chapter
Speaker: Dr. Kingsuk Maitra, AMD
Time: 6:00 PM – Pizza, 6:15 PM – Lecture
Cost: none
Place: National Semiconductor, Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

Recent advances of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look (more…)

Mtg: Internet Traffic Exchange – Future Directions

by @ 3:20 pm. Filed under ALL, Communications, Optics/Displays

TUESDAY March 18
SF Communications Chapter
Speaker: Bill Woodcock, Research Director, Packet Clearing House
Time: complimentary pizza/salad/desert dinner at 6:30 PM
Cost: none
Place: CCSF Downtown Campus, Fourth Street at Mission, San Francisco
RSVP: by email with Michael Butler, – 415-827-3680 for dinner count

A summary of the technological, economic, and policy issues related to internet traffic exchange.

Mtg: Research Techniques for the Consultant: Using the IEEE’s Xplore Database

by @ 3:18 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors

TUESDAY March 18
SCV Consultants’ Network of Silicon Valley
Speaker: Paul Wesling, VP-Publications, IEEE CPMT Society; Advisory Design Engineer, Hewlett Packard Corp (retired)
Time: Networking at 7:00 PM, followed by Presentation
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Avenue, Santa Clara
RSVP: not required

Consultants need to quickly understand previous technical developments and current difficulties associated with a proposed client project.? While some of this information can be obtained from specialists working for the client, and you may have considerable first-hand knowledge (more…)

Mtg: Home Digital Storage Hierarchy and Consumer Storage Demand

by @ 3:17 pm. Filed under ALL, Communications, Computers/Software, Electronics Design

TUESDAY March 18
SCV Magnetics Chapter
Speaker: Thomas M. Coughlin, Coughlin Associates
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required


This presentation discusses different mobile and static usage models for digital storage in consumer devices. ? These models define storage hierarchies that are useful for analyzing the proper digital storage technology for a consumer electronics application. (more…)

Mtg: Atomic Scale Modeling of Electron Transport in MRAM

by @ 3:16 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors

TUESDAY March 18
SCV Nanotechnology Chapter
Speaker: Dr. Dimitri Novikov, CTO, Atomistix, Inc.
Time: Registration & light lunch 11:30 AM, Presentation at Noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor, Bldg E-1 CMA Room, 2900 Semiconductor Drive, Santa Clara
RSVP: from the website


Atomic-scale modeling is becoming an important step in the process of designing novel advanced electronic devices, especially at the nanoscale size. Modeling R&D efforts are growing much faster (more…)

Mtg: Using Thermal Analysis as a Tool to Aid Analog Floorplanning

by @ 3:15 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

MONDAY March 17
SCV Circuits and Systems Chapter
Speaker: David Schwan, CAD and Layout Manager, RFMD
Time: Fast Food & drinks at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required

Todays’ IC designers are being driven to reduce area and increase performance and power-efficiency. Local circuit temperature can affect circuit performance, speed and current consumption, as well create reliability problems (more…)

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