IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

June 5, 2008

Mtg: MobileTV/Video Workshop

by @ 7:33 pm. Filed under ALL, Communications, Electronics Design

SCV Communications Chapter
Speakers: Christopher Dow, Director of Software, Macrovision; and others (Co-Sponsored by NATEA)
Time: 6:00 – 9:00 PM
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: not required


More details will be available on the website.


Mtg: Past, Present and Future of Solar Thermal Generation

by @ 7:30 pm. Filed under ALL, Electrical/Power, Engineering Mgmt

SF Power & Energy Chapter
Speaker: Bruce Kelly, P.E.
Time: Lunch and Presentation at Noon
Cost: Free for IEEE members, $5 for non-members
Place: Pacific Gas & Electric Office, 77 Beale St. Room 305, San Francisco
RSVP: by email to Anupama Pandey,, 415-369-1096


In response to the energy crisis of the early 1970â??s, the US Department of Energy initiated a range of R&D activities in central receiver, parabolic trough, and dish Stirling solar thermal technologies.? The most ambitious of the DOE activities was the 10 MWe, $150 million Solar One (more…)

Mtg: Congressional Insights, & Senior Member Upgrade Information Session

by @ 7:29 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors

SCV PACE – Professional Activities Committee for Engineers
Speaker: George Hanover, 2007 IEEE-USA Congressional Fellow
Time: Dinner and networking 6:00 PM, Senior Member Upgrade Information session at 6:45 PM, Presentation 7:00 PM
Cost: none (food, beverages can be purchased on-site)
Place: Grand Indian Buffet, 1214 Apollo Way, Sunnyvale
RSVP: not required


The IEEE PACE will have the honor of having George Hanover, 2007 IEEE-USA Congressional Fellow. He addressed innovation and competitiveness issues as a staffer for the Environment, Technology and Standards Subcommittee of the House Science Committee. (more…)

Mtg: Thermal Stress Modeling in Electronic and Photonic Engineering: Is FEA the Only Tool?

by @ 7:28 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays

SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Dr. Ephraim Suhir, CPMT Society Distinguished Lecturer; Bell Laboratories (ret); Dept of Electrical Engineering, UC-Santa Cruz; Dept of Mechanical Engineering, Univ of Maryland
Time: Seated dinner at 6:30 PM, Presentation (no cost) at 7:30 PM
Cost: $25 for dinner
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road, near Lawrence Expy), Sunnyvale
RSVP: by email to Janis Karklins,


This talk addresses the role and attributes of, as well as the state-of-the art and major findings in, the field of analytical thermal stress modeling in electronic and photonic engineering. The emphasis is on simple and practical models (more…)

Mtg: On Writing a Technical Book

by @ 7:26 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays

SCV Consultants’ Network of Silicon Valley
Speaker: Tom Coughlin, Coughlin Associates
Time: Networking at 6:30 PM, dinner at 7:00 PM, presentation at 8:00 PM
Cost: $20
Place: I Restaurant (Chinese), 20007 Stevens Creek Blvd (at Blaney Ave), Cupertino
RSVP: Use PayPal (through website), or mail a check and send an email RSVP

Just as many technologies converged to make magnetic disk drives ubiquitous, a similar but much more accelerated process has happened with the use of flash memory in the overwhelming success of todayâ??s consumer electronics (CE) devices. This success is best exemplified (more…)

Mtg: Integrated On-Chip Inductors Using Magnetic Material

by @ 7:25 pm. Filed under ALL, Communications, Electronics Design, NanoEngineering, Semiconductors

SCV Magnetics Chapter
Speaker: Don Gardner, Intel Corporation
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required


On-chip inductors with magnetic material are integrated into both advanced 130 nm and 90 nm CMOS processes. ? The inductors use copper metallization and amorphous CoZrTa magnetic material. ? Increases in inductance (more…)

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