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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

September 8, 2008

Mtg: Halogen Free Electronics

by @ 4:44 pm. Filed under ALL, BioEngineering, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY December 10, 2008
SCV Components, Packaging and Manufacturing Technology Chapter
Speakers: Dr. Dan Donahoe, Exponent; and Dr. Michelle Poliskie
Time: Seated dinner served at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by Dec 7; $30 after & at door; vegetarian available (no cost for presentation only)
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road at Lawrence Expressway), Sunnyvale
RSVP: by email to Janis Karklins, karklins@ieee.org
Web: www.cpmt.org/scv

Our talk will briefly explain why the environmental community has promoted the removal of halogens, what basic legislation is proposed and how industry standards are addressing the intersection of regulation and technology. ? We will discuss: (more…)

Mtg: 32 nm Node Optical Wafer Inspection: Perspectives and Challenges

by @ 4:35 pm. Filed under ALL, NanoEngineering, Optics/Displays, Semiconductors
 

TUESDAY October 21, 2008
SCV Nanotechnology Chapter
Speaker: Dr. Mehdi Vaez-Iravani, Senior Vice-President, KLA-Tencor
Time: Registration & light lunch at 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5. Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

The march toward ever shrinking design rules, and progress of IC manufacturing processes, have been facilitated in part by fast and precise techniques in wafer inspection and metrology.? In this talk I discuss the special challenges, and (more…)

Mtg: High Performance Digital Fractional-N Frequency Synthesizers

by @ 4:26 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY October 16, 2008
SCV Solid State Circuits Chapter
Speaker: Prof. Michael H. Perrott, MIT
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor, Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

Digital phase-locked loops provide many implementation advantages compared to their analog counterparts by avoiding large capacitors for loop filters and the complications of designing analog-intensive components such as charge pumps. ? A key question, (more…)

Mtg: Parallel Computing with CUDA on GPUs

by @ 4:04 pm. Filed under ALL, BioEngineering, Computers/Software, Engineering Mgmt
 

WEDNESDAY October 1, 2008
Monterey Bay Subsection
Speaker: Dr. John Nickolls and Dr. Massimiliano Fatica, Nvidia Corp.
Time: Refreshments and food at 6:00 PM; Presentation at 7:00 PM
Cost: none
Place: Simularium Room at the University of California in Santa Cruz, Room 180, Engineering Bldg 2, Santa Cruz
RSVP: by email to Marcelo Siero at siero@ee.com
Web: www.ee.com/gpu

The CUDA parallel programming model provides a straightforward means of describing inherently parallel computations. It lets programmers write scalable parallel programs with a minimal extension of the C language . NVIDIA’s Tesla GPU architecture (more…)

Mtg: Applied Innovation: How to Find the Next Big Thing in MedTech

by @ 3:45 pm. Filed under ALL, BioEngineering, Engineering Mgmt, NanoEngineering
 

WEDNESDAY September 17, 2008
SCV Engineering in Medicine and Biology Chapter
Time: Optional Dinner, Stanford Hospital Cafeteria, 6:15 pm (no host, no reservations); Presentation at Clark Center Auditorium at 7:30 PM
Cost: Free for presentation
Place: Clark Center Auditorium, Stanford University
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/embs

So you’d like to do something with your career that will make the world a better place for patients,. but where do you start? How do you find the next big opportunity in Medtech? Dr. Makower will share with you the secrets (more…)

Mtg: CEDIA and the Digital Home & Tour of HP Demo Home

by @ 3:33 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Optics/Displays, Semiconductors
 

TUESDAY September 23, 2008
SCV Consumer Electronics Chapter
Speaker: Gordon van Zuiden, President, cyberManor
Time: Pizza and drinks at 6:30 PM, Presentation at 7:00 PM, Tour at 8:00 PM
Cost: free for IEEE CES members, $5 for IEEE members, $10 for non-members
Place: Oak Room at HP, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ce

CEDIA is the Custom Electronics Design and Installation Association. This presentation will be on what a real digital home is like and how they work, sometimes with a million dollars of electronic equipment, followed by a tour of HP’s demo home. (more…)

Mtg: Photovoltaic Power Plant Design

by @ 3:06 pm. Filed under ALL, Electrical/Power, Electronics Design, Optics/Displays, Semiconductors
 

TUESDAY October 28, 2008
SF Industry Applications Chapter
Speaker: Charles Cunha, P.E., Square D, Inc.
Time: Social at 5:30 PM, Presentation at 6:00 PM, Dinner at 7:00 PM
Cost: $25 (pay at the door); $10 for Student Members
Place: Sinbadâ??s Restaurant, Pier 2 The Embarcadero, San Francisco
RSVP: by email to Jack Lin, jlin@sfwater.org, 415.551.4894
Web: www.e-grid.net/docs/0810-sf-ias.pdf

In this hour and a half presentation, our speaker will give an overview of how panel and inverter selection influences PV design, and also introduce array and field design issues. ? After a discussion of the NEC PV and utility interconnection (more…)

Embedded Power Conference (Sept. 17-18, 2008)

by @ 2:43 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

Embedded Power Conference [more]
— September 17-18, 2008 — San Jose Marriott Hotel
— Exhibits — Sponsored Tutorials –Keynote
Full information and registration: www.cmpegevents.com/web/pm

Technical Sessions: – Designing Your Own Power-down Tester – Improved Energy Efficiency Using Digital Power Architectures – Using a Digital Controller to Improve Power System Reliability – Is Thermal Design Power (TDP) the Best Metric Multi-Core
(more…)

Mtg: Location-Based Services: From Promise to Reality

by @ 2:40 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt
 

WEDNESDAY September 10, 2008
SCV Communications Chapter
Speaker: Ravi Jain, manager for mobile engineering, Google, & IEEE Fellow
Time: 6:30 PM
Cost: Donation to cover pizza
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/comsoc

Mtg: Novel Approaches to Low-Cost Solar Cells: Science and Challenges

by @ 2:40 pm. Filed under ALL, Electrical/Power, Optics/Displays, Semiconductors
 

WEDNESDAY September 10, 2008
SCV Components, Packaging and Manufacturing Technology + Women in Engineering Chapters
Speaker: Prof. Peter Peumans, Dept. of Electrical Engineering, Stanford Univ, and Deputy Director of the Center for Advanced Molecular Photovoltaics (CAMP)
Time: Dinner (optional) at 6:30 PM, Presentation at 7:30 PM
Cost: $25 if reserved by Sept. 8; $30 after & at door; no cost for presentation
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road at Lawrence Expressway), Sunnyvale
RSVP: by email to Janis Karklins, karklins@ieee.org

In this talk, I will discuss various approaches to harvesting solar energy that promise to lower the cost of solar electrical power. ? I will describe an approach that combines monocrystalline silicon with MEMS processing and advanced packaging (more…)

Mtg: Presentation by the Winner of IEEE Region 6 MicroMouse Contest 2008

by @ 2:39 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Optics/Displays, Semiconductors
 

TUESDAY September 9, 2008
SCV Electromagnetic Compatibility Chapter
Speakers: Josephine Sabado, Laura Biggs, Michael Miller, Mark Tuk and Harpreet Kaur, UC-Davis IEEE Student Branch MicroMouse Team
Time: 5:30 PM
Cost: none
Place: Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/emc

The presentation will focus on what the MicroMouse contest is and how the UC Davis team went about winning the contest. ? Issues include design decisions, group dynamics, and overall direction taken.? The team designed the MicroMouse (more…)

Mtg: A Brief History Of Magnetic Tape Recording At Ampex – 1944 To 1962

by @ 2:38 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY September 9, 2008
SCV Magnetics Chapter
Speakers: John M. Leslie and Jay McKnight, AMPEX (retired)
Time: Cookies, Conversation & Pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/mag

This talk covers the History of Magnetic tape recording at Ampex Corporation from its inception in 1944 to 1962. ? It includes highlights of: (1) what led a small motor manufacturer to become a major producer of magnetic tape recorders and an industry leader (more…)

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