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October 15, 2008

Mtg: Spice Model Extraction for Partially-Depleted SOI Technologies in Concurrent Designs

by @ 3:23 pm. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY November 11, 2008
SCV Electron Devices Chapter
Speaker: Dr. Brian Chen, Synopsis
Time: Social/food at 6:15 PM; Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building E-1, Conference Center, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Spice model extraction for partially-depleted (PD) silicon-on-insulator (SOI) technologies needs to address a number of technical challenges on top of those encountered in conventional bulk CMOS.? They include the self-heating effect, (more…)

Workshop: Smart Power Grid

by @ 3:11 pm. Filed under ALL, Electrical/Power
 

MONDAY November 3, 2008
SF Power & Energy Chapter
Speakers: from San Diego Gas and Electric, California Energy Commission, Electric Power Research Institute, Lawrence Berkeley National Laboratory, PG&E, and MegaWatt Storage Farms
Time: 8:00 AM – 4:30 PM
Cost: $100 IEEE Member, $150 Non-member, $25 Full Time Student with ID (includes continental breakfast, lunch)
Place: State of California Building, Benicia Room, 455 Golden Gate Avenue, San Francisco
RSVP: please prepay by check or PayPal (see website)
Web: ewh.ieee.org/r6/san_francisco/pes

Within the electric utility industry, the vision of a flexible and adaptive grid capable of meeting the energy needs of customers and supporting the clean energy solutions of tomorrow is referred to as Smart Grid.? This vision (more…)

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