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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

January 8, 2009

Mtg: Ramping 32nm High-Volume Manufacturing of Performance Logic in Record Time

by @ 4:34 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

TUESDAY January 20, 2009
SCV Electron Devices Chapter
Speaker: Dr. Hans Stork, CTO, Applied Materials
Time: Pizza at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor, Building E-1 Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

The transition to 32nm is happening as scheduled with 1.2 numerical aperture (NA) immersion lithography ready. There will not be disruptive technologies such as new substrates, biaxial stress and double gatesâ??rather, (more…)

Workshop: FPGAs for Digital Signal Processing Applications

by @ 3:58 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

SATURDAY February 7, 2009
SCV Signal Processing Chapter
Speakers: Dr. Xiaoshu Qian, Intel; Prof. Tokunbo Ogunfunmi, Santa Clara U; Dr. Chris Dick, Xilinx; Prof. Chang Choo, SJSU; Dr. Jim Hwang, Xilinx
Time: 8:00 AM – 5:00 PM
Cost: $70 for IEEE members, $80 for non-members, $30 for students (includes workshop proceedings, light breakfast, and lunch)
Place: Bannan Engineering Laboratories, Santa Clara University
RSVP: on the website
Web: ewh.ieee.org/r6/scv/sps/fpgaSPS

Topics at a glance:
8:00 AM: Registration
8:45 AM: “Why and when to use DSPs, FPGAs and ASICs,” Speaker: Dr. Xiaoshu Qian, Intel Corporation
9:20 AM: “FPGA Architectures for H.264 Video Processing,” Speaker: Prof. Tokunbo Ogunfunmi, Santa Clara University
11:00 AM: “FPGAs: Re-inventing the Signal Processor and MIMO-OFDM Applications,” Speaker: Dr. Chris Dick, Xilinx Corporation
1:30 PM: “FPGA-Based Embedded Wideband Audio Codec System,” Speaker: Prof. Chang Choo, San Jose State University
3:10 PM: “A Platform-Based Approach to Realizing High-Performance DSP Subsystems in FPGAs,” Speaker: Dr. Jim Hwang, Xilinx Corporation

Mtg: Dynamic Graphs

by @ 3:13 pm. Filed under ALL, Communications, Electronics Design
 

MONDAY January 12, 2009
SCV Signal Processing Chapter
Speaker: Dragoslav Siljak, Santa Clara University
Time: Fast Food & drinks at 6:30 PM; Presentation at 7:00 PM
Cost: $2 toward food
Place: National Semiconductor (north end of Building E), 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/sps

Dynamic graphs are defined in a linear space as a one-parameter group of transformations of the graph space into itself. Stability of equilibrium graphs is formulated in the sense of Lyapunov to study motions of positive graphs in the nonnegative orthant of the graph space. Relying on the isomorphism of graphs and adjacency matrices, a new concept of dynamic connective stability of complex systems is introduced. A dynamic interaction coordinator is added to complex interconnected system to ensure that the desired level of interconnections between subsystems is preserved as a connectively stable equilibrium of the overall system despite uncertain structural perturbations. It is shown how the coordinator can be designed to adaptively adjust the interconnection levels in order to assign a prescribed state of the complex multi-agent system as a stable equilibrium point. The equilibrium assignment is achieved by the action of the coordinator which solves an optimization problem involving a two-time-scale system; the coordinator action is slow compared to the fast dynamics of the agents. Polytopic connective stability of the multi-agent systems with a coordinator is established by the concept of vector Lyapunov functions and the theory of M-matrices.

Mtg: First SF-GOLD Chapter & Welcome Meeting of 2009

by @ 9:49 am. Filed under ALL, BioEngineering, Communications, Computers/Software, Electronics Design, NanoEngineering
 

THURSDAY February 5, 2009
SF GOLD (Grads of the Last Decade)? Committee
Event: an opportunity to network with fellow IEEE members and engineers, grab a bite and drink, and meet the officers
Time: 6:15 PM
Cost: none (except for your food/drink)
Place: “The Holding Company” 2 Embarcadero Center Promenade Level, San Francisco
RSVP: by email to Frank Oppong, sfgold.r6@gmail.com
Web: www.ewh.ieee.org/r6/san_francisco/gold

Happy new year!? Please join IEEE SF GOLD (Graduates of the Last Decade) for our first meeting of the year.? It will be an opportunity to network with fellow IEEE members, engineers and local Bay Area people, grab a bite and drink and meet with the officers of the club.

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