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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 1, 2009

Mtg: How to Make DAMN Good Decisions

by @ 4:09 pm. Filed under ALL, Engineering Mgmt

THURSDAY March 5, 2009
SCV Technology Management Council
Speaker: Burke Robinson, Ph.D., Consulting Professor, Stanford University
Time: Guided Networking at 6:30 PM; Dinner at 7:15 PM; Presentation at 7:45 PM
Cost: $25 for IEEE members; $30 for non-members ($5 more after 3/3)
Place: Ramada Inn, 1217 Wildwood Ave, Sunnyvale
RSVP: see web link (specify meat or vegetarian)

Burke Robinson is a consulting professor in the management science and engineering department at Stanford University.? He will present his Top Ten List for making DAMN good decisions.? Included on his list are: distinctions (more…)

Mtg: Semiconductor-laser Gain Physics: All you Want to Know and More in 50 Minutes

by @ 4:08 pm. Filed under ALL, Communications, Electronics Design, Optics/Displays, Semiconductors

TUESDAY March 3, 2009
SCV Lasers and Electro Optics Chapter – The Photonics Chapter
Speaker: Dr. Weng Chow, Sandia National Laboratories, IEEE LEOS Distinguished Lecturer
Time: Networking/Pizza Social 6:00 PM, Presentation at 7:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: see web link for EventBrite

This talk will start by sketching (with more pictures than equations) the formulation of a theory that is based on a systematic and consistent quantum mechanical description of a semiconductor laser medium.? The physical insight gained (more…)

Mtg: The Multi-Dimensional Design Space of Power, Reliability, Temperature and Voltage in Highly Scaled Geometries

by @ 4:06 pm. Filed under ALL, Communications, Computers/Software, NanoEngineering, Semiconductors

MONDAY March 2, 2009
SCV Circuits and Systems Chapter
Speaker: Fadi Kurdahi, Department of Electrical Engineering and Computer Science, UC-Irvine
Time: Networking & fast food at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required

Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of (more…)

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