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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 14, 2009

Workshop on Silicon Errors in Logic – System Effects

by @ 9:18 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors

IEEE Computer Society TC on Test Technology â?? SELSE 2009
Workshop on Silicon Errors in Logic – System Effects
– March 24-25, 2009 ? ? – Stanford University
The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. This workshop provides a forum for discussing current research and practice in system-level error management.
Topics: ? – New error mitigation techniques ? – Overhead and design complexity ? – Case studies ? – Experimental data ? – System-level models ? – Error handling protocols ? – Technology trends
Full information and registration:

Mtg: Energy Savings Programs â?? A Practical Approach to Implementation

by @ 9:14 am. Filed under ALL, Electrical/Power, Engineering Mgmt

THURSDAY March 19, 2009
OEB Industry Applications Chapter
Speaker: Finn Schenck, Integrated Building Solutions
Time: No-host social at 5:30 PM; Presentation at 6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM
Cost: $20 for IEEE members; $25 for non-members
Place: Marie Callender’s Restaurant – The Garden Room; 2090 Diamond Blvd, Concord (near the Concord Hilton)
RSVP: by March 18, by email to Gregg Boltz,, (925) 210-2571

The speaker will discuss several â??Easy to Implement??? energy saving opportunities, and review some of the tools available to monitor, measure, report on, and validate the success of energy saving (more…)

Mtg: Positive Feedback, Negative Feedback – A Closer Look at Phase Margin

by @ 9:11 am. Filed under ALL, Communications, Electronics Design, Semiconductors

THURSDAY March 19, 2009
SCV Solid State Circuits Chapter
Speaker: Prof. Bernhard E. Boser, EECS, UC-Berkeley
Time: Registration at 6:00 PM; Presentation at 6:30 PM
Cost: none (donation for food)
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: by email to

Feedback comes close to a “magic bullet” in the design of precision electronic circuits.? But behind the magic lurks possible catastrophe in the form of instability.? We will discuss stability criteria in the context of (more…)

Mtg: A Novel Technology to Improve the Effectiveness of Colonoscopy

by @ 9:10 am. Filed under ALL, BioEngineering, Electronics Design

WEDNESDAY March 18, 2009
SCV Engineering in Medicine and Biology Chapter
Speaker: Lex Bayer, VP of Product Development, Avantis Medical Systems
Time: Presentation at 7:30 PM
Cost: none — Optional Dinner, NEW LOCATION: Nexus Cafeteria in the Clark Center, 6:15 pm (no host, no reservations)
Place: Clark Center auditorium, Stanford University
RSVP: not required

Colorectal cancer is the second leading cause of cancer death in the United States. Adults 50 years of age and older are advised to routinely undergo colorectal cancer screening as a preventative measure. Much (more…)

Mtg: The Future of Cellular Infrastructure

by @ 9:09 am. Filed under ALL, Communications, Electronics Design

TUESDAY March 17, 2009
SCV Consultants’ Network of Silicon Valley
Speaker: Jonathan Wells, President, AJIS LLC
Time: 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required

The last few years have seen massive changes in the way we use cellular networks.? In addition to talking, we now take pictures, download music, record videos and manage and distribute them all over the (more…)

Mtg: Novel Nanomaterial-Enabled Devices for Sustainable Energy Harvesting and Utilization

by @ 9:08 am. Filed under ALL, Electrical/Power, NanoEngineering, Optics/Displays, Semiconductors

TUESDAY March 17, 2009
SCV Nanotechnology Chapter
Speaker: Dr. Bin Chen, Material Scientist, UC Santa Cruz / NASA Ames Research Center
Time: Registration & light lunch at 11:30 AM; Presentation at Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: via registration link on the website

Dr. Chen will discuss experimental approaches to synthesize hybrid nanocomposite materials.? These multifunctional nanomaterials are targeted for low cost and high efficiency power output for solar (more…)

Mtg: Condition Monitoring of Power Transformers using Dissolved Gas Analysis (DGA)

by @ 9:07 am. Filed under ALL, Electrical/Power

MONDAY March 16, 2009
SF Power & Energy Chapter
Speaker: Dr. Ahmad Shahsiah, senior engineer, Exponent, Inc (Failure Analysis Associates)
Time: Light lunch and talk at 12:00 PM Noon
Cost: Free for IEEE members, $5 for non-members
Place: Pacific Gas & Electric Office, 77 Beale St. Room 305, San Francisco
RSVP: by March 14 to John Joven,, 415-973-4873

Dissolved Gas Analysis (DGA) is a well-established method to monitor and predict the condition of devices with oil-cellulose insulation, especially power transformers. IEC 60599 defines characteristic (more…)

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