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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 24, 2009

Class: The Advanced World of Photovoltaics

by @ 7:31 pm. Filed under ALL, Electrical/Power, NanoEngineering, Optics/Displays, Semiconductors
 

Santa Clara University Graduate School of Engineering:
Emerging Topics in Engineering One-Day Program – April 27

The Advanced World of Photovoltaics (PV)?
The solar cell is the heart of photovoltaic systems â?? the device that converts sunlight to electricity. First demonstrated in the early 1950â??s, solar cells have undergone substantial evolution, with the best providing over 40% efficiency in the laboratory and over 20% in mass production. The objective is to provide an overview of recent trends in photovoltaics. This session covers advanced topics including improvements in solar cell design and manufacturing processes that lead to higher efficiency and lower cost, various thin film approaches, and concentrator cells and optics. Topics included: ? â?¢ Efficiency limits of solar cells ? â?¢ High efficiency silicon solar cell designs ? â?¢ Thin film approaches (Module design and manufacturing, Amorphous and micro-crystal silicon, CIGS, CdTe) ? â?¢ Concentrator cells and optics ? â?¢ Future approaches, including third generation and organic.
Register on the SCU Engineering website,? or contact Olivia Jenq, ojenq@scu.edu.

Embedded Systems Conference – Learn Today. Design Tomorrow.

by @ 7:17 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

Embedded Systems Conference – Learn Today. Design Tomorrow.
? ? — Mar 30 – Apr 3, 2009 ? ? — San Jose Convention Center
— Exhibits ? — 130 Sessions ? — Workshops ? — Tear-downs
ESC Silicon Valley is the must-attend event for embedded systems engineers — the largest gathering of 250+ exhibitors showcasing the latest embedded technologies available today.
Keynotes: ? – Adm. T.K. Mattingly, Apollo 13 astronaut ? – Steve Sanghi, CEO, Microchip Technology ? – Lisa Su, Senior V. P. and GM, CTO, Freescale
Features: ? – EE Times ACE Awards ? – Access to Live Product Teardowns ? – Executive Summit ? – Exhibits (Tues, Wed, Thurs) ? – Netrino Educational Sessions ? – Dev kits ? – Complimentary Exhibits Pass
Tracks: ? – Build Your Own Embedded System ? – Green Engineering ? – Datacom/Telecom ? – Real-Time Kernels ? – Consumer Electronics ? – Debug Techniques/Tools ? – Linux, Android, and Open-Source Software ? (and many more)
Register on our website: www.embedded.com/esc/sv ? – Use code PEGRID

Seminar: Hacking Your Professional Communication Style (career development)

by @ 5:56 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors
 

SATURDAY May 9, 2009
SCV Grads of the Last Decade (GOLD), with Women in Engineering (WIE) Chapters
Instructor: Steven Cerri, Career Coach/Consultant
Time: Registration and breakfast at 8:30 AM; Seminar from 9:00 AM – 3:30 PM
Cost: Early registration: $35 for IEEE Members, $40 for Nonmembers, $15 for Unemployed IEEE Member, $20 for other Unemployed. $60 at the door
Place: Qualcomm, 3165 Kifer Rd, Santa Clara
RSVP: by April 28 for best rates (higher fee after), using EventBrite from our website
Preview: YouTube, “Influencing Without Authority,” www.youtube.com/watch?v=YEQptFV9WTc
Web: www.ieee.org/scv/gold

As engineers, our process of influencing in technical organizations often revolves around data and information, not around our skill as communicators and persuaders.? But the short answer to this career challenge is (more…)

Mtg: Through-Silicon Vias (TSVs): Design and Reliability

by @ 1:44 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors
 

WEDNESDAY May 13, 2009
SCV Components, Packaging & Manufacturing Technology Chapter, with Electron Devices and Circuits & Systems
Speaker: Sergey Savastiouk, ALLVIA, Inc.
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by April 6; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website
Web: www.cpmt.org/scv

Thinned wafers with through-silicon isolated metal vias (TSVs) open a valuable new design opportunity for both IC and package engineers.? Through-silicon metal connectivity enables (more…)

Mtg: The Challenges and Rewards of Petascale Clusters

by @ 11:46 am. Filed under ALL, BioEngineering, Computers/Software, Semiconductors
 

THURSDAY April 30, 2009
OEB Computer Chapter
Speaker: Dr. Mark Seager, Lawrence Livermore National Laboratory
Time: Presentation at 6:30 PM
Cost: none
Place: Chevron (Bldg Bishop Ranch 1-X, Conference room #1220-1240 auditorium), 6101 Bollinger Canyon Road, San Ramon
RSVP: by 4/27 by email to Bill DeHope, dehope1@llnl.gov,
Web: www.e-grid.net/docs/0904-oeb-cs.pdf

Building, integrating and using petascale systems have many challenges including system power and cooling, system stability, scalablity, simulation environment and the development of petascale (more…)

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