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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

May 5, 2009

Seminar/Webinar: Green Reliability – What Comes Next?

by @ 4:12 pm. Filed under ALL, Electrical/Power, Electronics Design, Semiconductors

FRIDAY May 8, 2009
SCV Reliability Chapter?
Speakers: Dr. Cheemin BoLinn, Peritus Partners; Dr. Alan Wood, Sun Microsystems; Prof. Subhasish Mitra, Stanford University; Bryan Stallard, Ops A La Carte
Time: Registration at 8:30 AM; Seminar from 9:00 AM – Noon
Cost: none
Place: De Anza College, Conference Rooms A&B in the College Center, Cupertino; also simultaneously on the web
RSVP: see website

The IEEE Reliability Society, the ASQ Reliability Society and Ops A La Carte will be hosting a FREE seminar/webinar on GREEN RELIABILITY – some of the current trends as well as some of the issues and concerns around reliability in this rapidly expanding market. We will have the following presentations at the event (see website).

Mtg: IEEE Senior Member Grade Elevation Night

by @ 4:12 pm. Filed under ALL, BioEngineering, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors

THURSDAY June 4, 2009
SCV Section, IEEE
Activity: Upgrade from IEEE Member to Senior Member
Time: Drop in between 6:15 PM and 7:30 PM
Cost: none; refreshments provided
Place: Cogswell College, Executive Board Room, 1175 Bordeaux Drive, Sunnyvale
RSVP: not required – but complete the on-line form before coming

Mtg: Negative Bias Temperature Instability in p-MOSFETs: Fundamentals, Characterization, Materials Dependence and Modeling

by @ 2:24 pm. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors

TUESDAY June 9, 2009
SCV Electron Devices Chapter
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay (and EDS Distinguished Lecturer)
Time: Social/pizza at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Dr, Santa Clara
RSVP: not required

Negative Bias Temperature Instability (NBTI), causing shifts in device parameters such as drain current and threshold voltage, is a serious reliability concern for p-MOSFETs.? Though identified more than 40 years ago, NBTI has become the most severe front-end reliability issue only recently, as gate oxide thickness is scaled below 2nm, and Nitrogen is incorporated into the gate oxide to prevent Boron penetration and leakage.? Besides Si oxynitride/poly-Si devices, NBTI is also a serious concern for high-k/metal gate devices as well.
Like other reliability issues (such as HCI), device lifetime under NBTI is determined by accelerated stress tests done at short times, and extrapolating the degradation under operating conditions to end of life.? It is very important to choose proper stress conditions such that defects responsible for NBTI are only accelerated and no new defects are formed.? As NBTI degradation recovers (unlike HCI) after stress is turned off for measurement, conventional stress-measure-stress methods give erroneous results, and fast methods must be implemented.? It is important to understand and model the NBTI physical mechanism, so that proper physics-based models can be developed for reliable determination of device lifetime.? It is also important to understand the process/material dependence of NBTI to develop robust, NBTI-safe gate insulators that meet other (leakage, mobility) requirements.? The talk will address some of these issues.

Mtg: Molecular Modification of PCB Substrates for Fine Line Patterning

by @ 10:01 am. Filed under ALL, Electronics Design, NanoEngineering

WEDNESDAY September 9, 2009
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Werner Kuhr, Ph.D., VP-Research, ZettaCore, Inc., Englewood, CO
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by Sept 7; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website

ZettaCore has developed a new Molecular Interfaceâ?¢ technology, where a molecular adhesion layer is created for smooth epoxy substrates to allow the electroless deposition and electroplating of copper onto (more…)

Mtg: Goldilocks and the Three Bears: Two Case Studies of Optimal Development Processes for Startups, Large Companies

by @ 7:30 am. Filed under ALL, Engineering Mgmt

THURSDAY June 4, 2009
SCV Technology Management Chapter
Speaker: John Carter, Principal, TCGen Inc.
Time: Guided Networking at 6:30 PM, Sandwiches/drinks at 7:15 PM, Presentation at 7:45 PM
Cost: $10 (IEEE member), $13 (non member) (add $3 without reservation)
Place: Ramada Inn, 1217 Wildwood Ave, Sunnyvale
RSVP: through the website

How much process is just right for a rapidly scaling software development organization?? Too much process can stifle creativity and slow down development, resulting in products that miss the market.? Too little (more…)

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