IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

June 10, 2009

Mtg: Synthesis and Applications of Carbon Nanotubes and Nanofibers

by @ 3:44 pm. Filed under ALL, Electronics Design, NanoEngineering, Optics/Displays, Semiconductors

TUESDAY July 21, 2009
SCV Nanotechnology Chapter
Speaker: Brett A. Cruden, Ph.D., NASA Ames University Affiliated Research Center
Time: Registration & light lunch 11:30 AM, Presentation at 12:00 Noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: via the website

Carbon nanotubes have generated significant interest in recent years due to their remarkable physical properties, being stiffer than diamond, higher yield strengths than any other material, thermal (more…)

Free Webinar: Making the Electric Grid Smarter, Stronger, Greener, and More Secure

by @ 2:45 pm. Filed under ALL, Electrical/Power, Electronics Design

TUESDAY June 23, 2009
Speaker: Dr. Massoud Amin, Director, Center for the Development of Technological Leadership, University of Minnesota
Time: 11:30 AM – 12:30 PM, PDT
Cost: none
Place: on the Web
RSVP: register on the GoToMeeting website

The North American Electric Grid is considered to be the worldâ??s largest machine as well as one of the 20th centuryâ??s greatest technological achievements.? However, this same magnificent grid has (more…)

2009 IEEE Honors Ceremony: Celebrating 125 Years of Engineering the Future

by @ 1:36 pm. Filed under ALL

THURSDAY June 25, 2009
Hosts: John R. Vig, 2009 IEEE President, with Pedro A. Ray, 2009 IEEE President-Elect
Time: 6:00 PM
Cost: none
Place: on the Web
RSVP: not required

For the first time, the IEEE Honors Ceremony will be broadcast live on the Web through The 2009 Honors Ceremony will take place Thursday, 25 June at the Hyatt Regency Century Plaza in Los Angeles, Calif. at 6 p.m. Pacific Time. (more…)

Tour: Trans Bay Cable Project 400 MW High Voltage Direct Current (HVDC) System

by @ 9:00 am. Filed under ALL, Electrical/Power

THURSDAY July 16, 2009
OEB Power & Energy, with SF Industry Applications Chapter
Speaker: Siemens staff. The tour is limited to 30 people.
Time: Presentation at 10:30 AM (includes lunch); Depart to tour at 11:45 AM; Tour from Noon – 1:00 PM
Cost: $20 for IEEE members, $15 for the first 5 IEEEstudent members, $35 for non-members
Place: Liberty Hotel Restaurant, 200 E 3rd St, Pittsburg
RSVP: Reservations are required due to limitations on tour size. By email to

Siemens will provide a presentation on the system and a walking tour around the converter station.? While still under construction, the various systems and subsystems are already installed.? The group (more…)

Conf: 46th IEEE Design Automation Conference (DAC)

by @ 8:01 am. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

Where electronic design meets …
46th IEEE Design Automation Conference (DAC)
— July 26-31, 2009 ? ? — Moscone Convention Center, SF
— 50 technical sessions, 150 papers ? ? — 200 Exhibitors
— 8 Workshops ? ? — 6 Tutorials ? ? — 8 Panels
DAC is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. Learn more about system-level design, embedded systems, multicore, low power, physical design and manufacturing, new and emerging technologies, verification and test, and more. The all-new User Track (9 sessions) focuses on problems that design practitioners face every day. Keynotes; Management Day; topical Pavilion Panels; Exhibitor Forum; 11 co-located events.
Register by June 29 for only $410 (IEEE members). Make plans today!
More information:

Mtg: Advanced Lithography Techniques for 22nm Half-pitch and Beyond

by @ 7:27 am. Filed under ALL, NanoEngineering, Optics/Displays, Semiconductors

TUESDAY August 4, 2009
SCV Photonics Chapter
Speaker: Dr. Yashesh A. Shroff, Intel
Time: Networking/Pizza Social at 6:00 PM, Presentation at 7:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: via the website

Immersion lithography has become the mainstay of 45nm and below half-pitch nodes, having overcome a number of challenges on the way to high volume manufacturing.? Significantly, extensions to (more…)

Position: Electrical Engineer with P.E. License

by @ 7:15 am. Filed under ALL, Electrical/Power

Position available in San Francisco
Electrical Engineer with P.E. License
– Mazzetti Nash Lipsey Burch ? – Located in SF
Qualifications: ? â?¢ Project management-level experience; â?¢ designing electrical and lighting systems for buildings; â?¢ Producing contract documents and specifications; â?¢ Stable and meaningful work history; â?¢ Ability to work on complex projects with general direction; â?¢ Versatility, flexibility with constantly changing priorities.
We provide excellent benefits, including quarterly bonuses, 401K match at 20%, health/dental/vision/life/flex insurance, employee stock ownership, and academic/professional fee assistance. For full position description, visit “Careers” at

Conf: CMOS Emerging Technologies Workshop

by @ 7:13 am. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors

Theme: Research & Business Opportunities Ahead
CMOS Emerging Technologies Workshop
— September 23-25, 2009 ? ? — Vancouver, BC, Canada
This research and business event is for those who want to discuss and discover new and exciting high-tech opportunities. The format of the talks resembles in-depth tutorials describing state-of-the-art technology and future research directions. The 6th annual workshop will be held downtown Vancouver with numerous opportunities for personal exploration of surrounding tourist attractions.
Sessions: ? – Communications ? – Biomedical Circuits ? – Wireless ? – Nanoelectronics ? – Microsystems ? – RF Circuits ? – Mixed-Signal ? – I/O Circuits ? – Optical/Medical Imaging ? – Photonics ? – VLSI ? – SOC ? – Radiation Detectors/Imagers ? – Circuits for Radiation ? – Silicon Technology ? – Programmable Devices ? – EDA Design Tools ? – Business Development
Registration is now open! Plan to attend … ?

Conf: Flash Memory Summit

by @ 7:12 am. Filed under ALL, Communications, Computers/Software, Electronics Design, NanoEngineering, Semiconductors

4th Annual Flash Memory Summit
– August 11-13, 2009 ? – Santa Clara Convention Center
– Tutorials ? – Exhibits ? – Sessions
This power-packed 3-day event covers the latest topics in flash memory. Hear about flash in embedded systems, laptop design, flash in enterprise storage systems, green flash, solid state drives, flash performance, flash-based design, flash in computers, mobile applications, software, new non-volatile memory technologies, reliability, security, and much more!
Earlybird rates through August 6
Save $100 – use Registration Code “IEEE”
Visit the website:

Conf: InterPACK’09 – Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS

by @ 7:10 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors

InterPACK’09: Conf. on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS
– July 19-23, 2009 ? – Westin St Francis, SF
Focus of InterPACK: ? â?¢ Advanced Packaging ? â?¢ Electro-Thermal-Mechanical Issues in Packaging (Multi-Physics) ? â?¢ Materials and Processes ? â?¢ MEMS and MEMS Packaging ? â?¢ Manufacturing and Test ? â?¢ Modeling and Simulation ? â?¢ Nanotechnology and NEMS ? â?¢ Photonics and Optics ? â?¢ Reliability ? â?¢ Thermal Management ? â?¢ Emerging Technologies
Co-located with ASME Summer Heat Transfer Conference and ASME Energy Sustainability Conference
Visit the website:

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