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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

August 14, 2009

Call for Nominations for IEEE Fellow

by @ 5:57 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power, Electronics Design, Engineering Mgmt

Call for Fellow Nominations
Nominations are being accepted for the IEEE Fellows class of 2011. The rank of IEEE Fellow is the institute’s highest member grade, bestowed on an IEEE Senior Member who has had an extraordinary record of accomplishments in any of the IEEE fields of interest. The deadline for nominations is 1 March 2010. Senior Members can be nominated in one of four categories: application engineer/practitioner, research engineer/scientist, educator, or technical leader. The Fellows Web pages contain information regarding the nomination process, access to the Fellows Nomination Kit, lists of Fellows who are eligible to be references and more about the Fellow program. We recommend that you use the Electronic Fellow Nomination Process (EFNP). Please visit the Fellows website at
Newly elected Fellows for 2009 will be announced following the IEEE Board Meeting in November.

Int’l Symposium for Testing and Failure Analysis (ISTFA)

by @ 5:56 pm. Filed under ALL, Electronics Design, NanoEngineering, Optics/Displays, Semiconductors

Theme: It’s All About Resolution.
35th Int’l Symposium for Testing and Failure Analysis
— November 15-19, 2009 ? ? — San Jose Convention Center
— Sessions: Tues-Thurs, Nov 17-19 ? ? — Exposition: Tues-Wed, Nov 17-18
ISTFAâ??09 combines technical sessions, tutorials, an exhibition, and user group meetings with a focus on making the full experience a strong benefit for the attendee.
Sessions: ? – Emerging Concepts ? – Photon Beam-based Techniques ? – Nanoprobing ? – Circuit-edit ? – Sample Preparation ? – Alternative Energy Photovoltaic FA ? – Failure Analysis Process ? – Packaging/Assembly Level FA ? – Photon Beam-based Techniques ? – Advanced Metrology and System Level FA ? – plus Panel Discussion, Poster Papers
Plus Tutorials, six Short Courses, exhibits. ? Register by Sept 18 â?? Save up to $200.
Download the Advance Brochure … ?

Embedded Systems Conference – Boston

by @ 5:53 pm. Filed under ALL, Communications, Computers/Software, Electronics Design

Embedded Systems Conference – Boston
— September 21-24, 2009 ? ? ? — Tutorials, Exhibits
— Practical design information you can use today. Skills you use for a lifetime.
ESC-Boston brings together the systems design community for eye-to-eye communication on real-world solutions, with exhibitors across the embedded industry with the tools you need, and solution-swapping opportunities with your peers in discussion groups.
20 Technical Tracks: ? – C and C++ ? – Commercial & Open-Source OSs ? – Consumer Electronics ? – Debugging and Verification ? – Designing for Power Efficiency ? – Graphics, Displays and Lighting ? – Multi-core, Multi-threading, and Virtualization ? – Multimedia and Signal Processing ? – Sensors (including MEMS) ? – System Integration and Test ? – Wired and Wireless Technologies ? – Build Your Own Embedded System (with an Intel Atom-based kit) ? and more!
Full-day Tutorials: ? – High Availability Embedded Systems ? – Hardware Interfacing in C ? – Embedding TCP/IP ? – Real-Time Kernels ? – Managing Embedded Projects
Use code “IEEE10” for a 10% discount.
For full details:

EOS/ESD Symposium & Exhibits

by @ 5:49 pm. Filed under Electronics Design, Engineering Mgmt, Semiconductors

31st Annual EOS/ESD Symposium & Exhibits
The Technical Forum on Electrical Overstress and Electrostatic Discharge
— August 30-September 4, 2009 ? ? — Disneyland Hotel, Anaheim
— 15 Technical Sessions ? ? — 10 Workshops ? ? — Exhibits
Basic, intermediate, and advanced tutorials; exhibits of ESD control products and services; workshops; authors’ corners; Program Manager Certification; Device/Design Certification.
27 Tutorials on ? Basics, On-Chip Protection, Evaluation Measurements, Latch-up Physics, Technology Scaling, ESD Failures ? and much more.
Sessions on Component Testing; System Level Testing; On-Chip Protection; Numerical Simulation, Modeling, Reliability; Extremely Sensitive Devices; MR-Heads, MEMS; On-Chip ESD Failure Case Studies ? and more.
New lower hotel rates! Bring the family.
Download the Advance Program:

Mtg: A 32 Gbps 2048-bit 10GBASE-T Ethernet Energy Efficient LDPC Decoder with Split-Row Threshold Decoding Method

by @ 3:18 pm. Filed under ALL, Communications, Electronics Design, Semiconductors

THURSDAY August 20, 2009
SCV Solid State Circuits Chapter
Speaker: Tinoosh Mohsenin, University of California, Davis
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

Low density parity check (LDPC) codes have received significant attention due to their superior error correction performance, and have been considered by emerging communication (more…)

Mtg: Sub-wavelength Dielectric Gratings: A New Handle On Light

by @ 3:16 pm. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors

WEDNESDAY August 19, 2009
SCV Nanotechnology Chapter
Speaker: Dr. David Fattal, Staff Researcher, HP Labs
Time: Registration & light lunch 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: via the website

Dielectric gratings exhibiting resonance phenomena have been studied since the early 90’s, offering a new paradigm for optical filtering and sensing.? More recently, they have been (more…)

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