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September 28, 2009

Mtg: Reverse Engineering in the Semiconductor Industry

by @ 4:29 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY November 16, 2009
SCV Circuits and Systems Chapter
Speaker: Randy Torrance, Chipworks
Time: Networking/Pizza at 6:30 PM, Presentation at 7:00 PM
Cost: $2 donation for food
Place: Cadence Design Systems, Building 5, 2655 Seely Avenue, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas (scroll down)

The continuous drive of Moore’s law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns and demanding the (more…)

Mtg: Nanopackaging: Nanotechnologies in Microelectronics Packaging

by @ 4:28 am. Filed under ALL, BioEngineering, Electronics Design, NanoEngineering, Optics/Displays, Semiconductors
 

WEDNESDAY November 11, 2009
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: James E. Morris, Department of Electrical & Computer Engineering, Portland State University, and CPMT Society Distinguished Lecturer
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by Nov 9; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website
Web: www.cpmt.org/scv

While the electronics industry continues to look for the next nanoscale device to take over from the MOSFET, other nanotechnologies are already being developed for microelectronics packaging, primarily (more…)

Seminar: Impact of Packaging Materials and Processes on Device Soft Error Rates

by @ 4:24 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

FRIDAY October 30, 2009
SCV Components, Packaging and Manufacturing Technology, with Electron Devices and Reliability Chapters, and ASQ Reliability Division
Speakers: from Cisco Systems, Honeywell, XIA, ASE, Sun Microsystems, and Medtronic
Time: Registration at 8:45 AM; Presentations and Panel from 9:00 AM – 12:00 Noon
Cost: none
Place: Live on the Internet through WebEx; also in-person at Cisco Building O, 10 West Tasman Drive (at corner of N. First St), San Jose
RSVP: Required, by October 28, on our DoubleKnot site; on-site seating is limited
Web: www.cpmt.org/scv

Half-day Seminar with six talks:
“Impact of Substrate SOP on Flip Chip Soft Error Rates,” Rick Wong, Cisco Systems
“Progress Towards (more…)

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