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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

July 16, 2010

Mtg: Legal Documents 101: Everything You Need to Know to Operate a Successful Consulting Practice

by @ 6:20 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, NanoEngineering

FRIDAY July 23, 2010
SCV Consultants’ Network of Silicon Valley
Speakers: Jonathan Sweet, JD; Lonnie Finkel, JD
Time: 8:30 AM to 12:30 PM
Cost: IEEE Members $47; Non-Members $67
Place: Cogswell Polytechnical College, 1175 Bordeaux Drive, Sunnyvale (also as a Webinar)
RSVP: required – from the website

Mtg: A Picture is Worth a Thousand (DRC) Rules

by @ 6:20 pm. Filed under Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors

TUESDAY July 20, 2010
SCV Nanotechnology Chapter
Speaker: Michael White, Sr Product Manager, Calibre Physical Verification Products, Mentor Graphics
Time: Registration & light lunch at 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: required – from the website

New manufacturing issues have a huge effect on how we do IC physical verification at the leading nodes.? Design rule checking has changed from simple one-dimensional spacing and width checks to complex 3D geometrical functions covering (more…)

Tour: AT&T Park Tour (and Giants vs. Mets)

by @ 6:18 pm. Filed under ALL, Communications, Electrical/Power, Engineering Mgmt

SATURDAY July 17, 2010
SF Power & Energy Chapter
Time: Tour: 2:30 – 4:00 PM. Game: 6:00 – 9:00 PM
Cost: $5 for IEEE members, $15 for non-members, Free for children under 2 (game is add’l $16 for IEEE members, $32 for non-members)
Place: AT&T Park, 24 Willie Mays Plaza, San Francisco
RSVP: Space is limited. Please contact John Joven, for more information: 415-973-4873

Mtg: Embedded Passives: Packaging Paradigm of the Future?

by @ 6:17 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

WEDNESDAY November 10, 2010? (postponed from 9/8)
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Jason Ferguson, Crane Naval Surface Warfare Center
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20 for dinner; Students & unemployed members $10 (no cost for presentation-only)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: From the website

Embedded Passive (EP) Technology is of interest to many OEMs and designers, but the technology remains a mystery for how and when to implement this technology into designs.? This presentation will reveal what EP materials are out on (more…)

Mtg: High-Speed Transmission on Twisted Pair in LANs and DSL

by @ 6:14 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors

WEDNESDAY September 8, 2010
SCV Communications Chapter
Speakers: Sanjay Kasturia and Jose Tellado, Teranetics; George Ginis, ASSIA, Inc
Time: Networking with refreshments at 6:00 PM; Presentations at 6:30 PM, followed by panel
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: From the website

This session will address the challenges of high speed twisted pair-based communications in data centers/enterprises (LAN) and wireline access (DSL).? There will be two talks followed by a panel session/audience Q and A.? The panel (more…)

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