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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

September 23, 2010

Mtg: Low Power Design for Open Wireless Architecture (OWA) Baseband Processor supporting Various Wireless Standards

by @ 12:06 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY November 15, 2010
SCV Circuits and Systems Chapter
Speaker: Prof. Willie W. Lu, CEO, China 4G Labs
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

The OWA family of programmable and open baseband processors is designed for hosting multiple wireless standards of mobile communication, wireless connectivity, and reception of broadcast services in one common platform.? The OWA Processors (more…)

September 20, 2010

Mtg: Smart TVs and other CE innovations from the Intel Developer Forum

by @ 1:46 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

TUESDAY September 28, 2010
SCV Consumer Electronics Chapter
Speakers: Mike Demler; and Tom Coughlin, President, Coughlin Associates
Time: Pizza and drinks at 6:30 PM; Presentations at 7:00 PM
Cost: IEEE members $5; non-members $10
Place: NVIDIA, 2800 Scott Blvd – Building E, Santa Clara
RSVP: EventBrite, from website
Web: www.ewh.ieee.org/r6/scv/ce

This will be a review of consumer electronics innovations on display at the recent Intel Developer Forum – including Google-TV, new tablet PCs based on MeeGo and Windows-7, and a gesture-based UI (more…)

Mtg: Smart Computing for the Smart Grid

by @ 1:17 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power
 

TUESDAY November 9, 2010
SCV Computer Chapter, with Power & Energy Chapter
Speaker: Rick Geiger, Executive Director, Cisco
Time: Networking with food and beverage at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation for food
Place: Microsoft Research (use rear/North door), 1288 Pear Ave., Mountain View
RSVP: required – from the website
Web: smartergrid.eventbrite.com

Computing content for the Smart Grid is highly varied.? Smart Grid has many aspects.? From a compute standpoint, the most challenging is in modeling and managing the change from a bulk power distribution (more…)

Smart Grid Workshop: M2M Communications, Emerging Devices and “The Internet of Things”

by @ 11:10 am. Filed under ALL, Communications, Electrical/Power, Electronics Design
 

SATURDAY September 25, 2010
SCV Communications Chapter, with NATEA
Speakers: Claudio Lima, IEEE P2030 Smart Grid Architecture Standards WG; Stefano Galli, Panasonic R&D; Kuor-Hsin Chang, Elster Solutions; Jeffrey Smith, Numerex Corp, Jason Porter, AT&T; Michael Finegan, Sprint Emerging Solutions Group
Time: Presentations from 1:00 PM – 7:00 PM in two tracks
Cost: IEEE Members, students, unemployed $10; non-members $20
Place: Benson Center, Santa Clara University, Santa Clara
RSVP: From the website
Web: www.ewh.ieee.org/r6/scv/comsoc

Mtg: Object Bank: An Object-Level Image Representation for High-Level Visual Tasks

by @ 11:09 am. Filed under ALL, Communications, Computers/Software, Optics/Displays
 

THURSDAY September 23, 2010
SCV Robotics and Automation Chapter
Speaker: Jia Li, Stanfor University
Time: Presentation at 7:00 PM
Cost: none
Place: Carnegie Mellon University – SV, NASA Research Park, Bldg. 23, Moffett Field
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ras

Robust low-level image features have been proven to be effective representations for a variety of tasks such as object recognition and scene classification; but pixels, or even local image (more…)

Mtg: Successful Applications of MoM/MLFMM to Antennas Located on Vehicles

by @ 11:07 am. Filed under ALL, Electronics Design
 

THURSDAY September 23, 2010
SCV Antennas and Propagation Chapter
Speaker: Thomas Tarter, Package Science Services LLC
Time: Networking/refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: Cogswell College, 1175 Bordeaux Drive, Sunnyvale
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/aps

Mtg: Design of High Density & 3D Packaging: Tools and Knowledge

by @ 11:06 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY September 23, 2010
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Thomas Tarter, Package Science Services LLC
Time: Registration & social at 11:30 AM; Optional lunch at 11:45 AM; Presentation at 12:15 PM
Cost: $15 for lunch; Students & unemployed members $5 (no cost for presentation-only)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: From the website
Web: www.cpmt.org/scv

Packaging of complex silicon devices requires a deep knowledge of many aspects of high-technology engineering disciplines.? As an example, packaging a high lead-count chip requires (more…)

Webinar: Hall Effect Measurements for Semiconductors

by @ 11:05 am. Filed under ALL, Electronics Design, Optics/Displays, Semiconductors
 

THURSDAY September 23, 2010
SPECTRUM Magazine ?
Speaker: Robert Green, Senior Market Development Manager, Keithley Instruments
Time: 1-hour Presentation at 11:00 AM PDT
Cost: none
Place: On the Web
RSVP: on the website
Web: spectrum.ieee.org/webinar/1668651

Webinar: High Fidelity Physical Models of Automotive Batteries

by @ 11:04 am. Filed under ALL, Electrical/Power, Electronics Design
 

WEDNESDAY September 22, 2010
SPECTRUM Magazine
Speakers: Dr. Tom Lee, Vice President, Maplesoft; Dr. John McPhee, Chair for Mathematics-based Modeling, University of Waterloo; Dr. Thanh-Son Dao, Dept. of Systems Design Engineering, University of Waterloo
Time: 1-hour Presentation at 11:00 AM PDT
Cost: none
Place: On the Web
RSVP: on the website
Web: spectrum.ieee.org/webinar/1679787

Mtg: California Emerging Technology Fund

by @ 11:03 am. Filed under ALL, Communications, Electronics Design
 

TUESDAY September 21, 2010
SF Communications Chapter
Speaker: Susan E. Walters, California Emerging Technology Fund
Time: Lasagne and salad dinner at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: California Public Utilities Commission, 505 Van Ness Ave (use Golden Gate entrance), San Francisco
RSVP: my email to timryan@ieee.org
Web: www.ieee.org/sfcomsoc

California Emerging Technology Fund will present an overview of its background, strategic focus, current activities and accomplishments in closing the Digital Divide in a way that (more…)

Mtg: Thermally-Assisted Magnetic Recording at up to 1 Tb/in2 using an Integrated Plasmonic Antenna

by @ 10:51 am. Filed under Computers/Software, Electronics Design, NanoEngineering, Semiconductors
 

TUESDAY September 21, 2010
SCV Magnetics Chapter
Speaker: Barry Stipe, Hitachi Global Storage Technologies
Time: Networking and pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/mag

Thermally-Assisted Magnetic Recording (TAR) and Bit Patterned Recording (BPR) are two of the most promising technologies for surpassing the fundamental limitations of conventional magnetic recording. In a typical TAR head design, a waveguide delivers light to a plasmonic aperture or antenna located at the air-bearing surface.? The plasmonic device creates an intense optical pattern in the near-field, heating the disk at the nanometer scale.? This writing technique allows one to use extremely high anisotropy media (such as L10 FePt) for reduced grain size while maintaining the requirements of thermal stability and writability.? We have fully integrated a plasmonic antenna called the â??E-antenna??? into a magnetic head and then used it for recording on granular media with a static tester and spin stand.
So far, TAR at over 400 Gb/in2 has been limited by the availability of a suitable small grain media.? BPR avoids the need for small grain media but it can be difficult to address the patterned bits at very small track pitch using a conventional write head.? We have recently found that combining TAR and bit-patterned media (BP-TAR) can solve both problems and allows for dramatic reductions in track pitch (down to 24 nm) and optical power requirements (factor of five) as compared to TAR recording on granular media.? We show recording at up to 1 Tb/in2.? BP-TAR may turn out to be the ultimate HDD technology and is, in principle, scalable to 100 Tb/in2.

Mtg: SolFocus Concentrator Photovoltaics â?? An Introduction

by @ 10:48 am. Filed under ALL, Electrical/Power, Electronics Design
 

TUESDAY September 21, 2010
SCV Nanotechnology Chapter
Speaker: Dr. Phil Metz, Director of Business Development, SolFocus
Time: Registration & light lunch 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

This presentation introduces the SolFocus Concentrator Photovoltaic (CPV) product â?? what it is and how it works.? It presents the value proposition for SolFocus CPV and the design and (more…)

Mtg: Silicon Photonics: Opportunities & Challenges

by @ 10:47 am. Filed under ALL, Communications, Optics/Displays, Semiconductors
 

MONDAY September 20, 2010
SCV Circuits and Systems Chapter
Speaker: Dr. Haisheng Rong, Senior Scientist, Intel Labs
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

Silicon photonics technology offers promising low-cost optoelectronic solutions for many applications ranging from optical communications to emerging areas such as optical sensing and (more…)

September 11, 2010

Mtg: Shingled Magnetic Recording and Two-Dimensional Magnetic Recording

by @ 5:07 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Optics/Displays
 

TUESDAY October 19, 2010
SCV Magnetics Chapter
Speaker: Roger Wood, Hitachi Global Storage Technologies
Time: Networking and Pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/mag

Magnetic recording as we know it today is approaching its theoretical limit of about 1 Terabit/in2.? Annual increases in HDD capacity will come to a halt unless a significant new technology can be introduced (more…)

Mtg: Solving Radio Frequency Interference Problems

by @ 4:46 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt
 

WEDNESDAY October 20, 2010
SCV Instrumentation & Measurement Chapter
Speaker: Steve Thomas, Senior Product Manager, Anritsu Company
Time: Networking and refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: Board Room, Cogswell College, 1175 Bordeaux Drive, Sunnyvale
RSVP: by email to brian.lee@ieee.org or 408-201-1976
Web: www.ewh.ieee.org/r6/scv/ims

As wireless systems proliferate worldwide, the number one enemy of wireless systems designers and service providers is signal interference. Interference hampers coverage and capacity, and limits the effectiveness (more…)

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