IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

October 15, 2012

Mtg: Antenna Synthesis: A New Way to Approach Antenna Design

by @ 7:28 am. Filed under ALL, Communications, Electronics Design

THURSDAY October 18, 2012
SCV Antennas and Propagation? Chapter
Speaker: Dr. Jason Lohn, Associate Professor, Carnegie Mellon University Silicon Valley
Time: Networking with food at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: Carnegie Mellon University, Building 23, Moffett Field
RSVP: from website

Current methods of designing and optimizing antennas by hand are time and labor intensive, limit complexity, and require significant expertise and experience.? AI search algorithms can overcome these limitations by automatically searching the design space and finding effective solutions that are closer to limits imposed by physics.? For example, our algorithms have discovered counter-intuitive antenna designs that out-perform traditionally designed systems.? While optimization modules are commonly available in commercial RF CAD tools, they are typically simple parametric methods, and no system yet offers an antenna synthesis capability.? We discuss the antenna synthesis system we are developing and its use in a variety of applications,? including a project that produced antennas that flew in space on NASAâ??s Space Technology 5 (ST5) mission.

Mtg: Addressing the Grid Integration Challenges of High-Penetration Photovoltaic Systems

by @ 7:26 am. Filed under ALL, Electrical/Power, Optics/Displays

THURSDAY October 18, 2012
OEB Industry Applications Chapter
Speaker: Robert Johnson, SunPower
Time: Networking at 5:30 PM; Presentation at 6:15 PM; Dinner at 7:15 PM; Presentation continues after dinner
Cost: $25 for IEEE members; $30 for non-members; $15 for student and retired members
Place: Zio Fraedos, 611 Gregory Lane, Pleasant Hill
RSVP: by email by October 15 to Michael Nakamura, or call 510-287-2066

The rapidly growing penetration of photovoltaic power systems poses new technical and policy challenges as we work to integrate these distributed and variable generation resources into our electrical grids.? This presentation will look in detail at various supervisory control and data acquisition (SCADA) systems and applications used to address these challenges.? These include automatic voltage regulation, curtailment control, synchrophasors, and others.? It will also examine the interconnection requirements and system performance characteristics driving these applications.
This presentation will look at aspects of Utility-Scale PV system configurations and design, modeling and validation, system dynamics, communication and control infrastructure, and other related topics.

Mtg: Accelerating Analog Design

by @ 7:24 am. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors

THURSDAY October 18, 2012
SCV Solid State Circuits, with Professional Activities Committee for Engineers (PACE)
Speaker: S. S. Mohan, Synopsys
Time: Networking with pizza at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: TI Auditorium E, 2900 Semiconductor Drive, Santa Clara
RSVP: from website

We investigate state-of-the art technology that accelerates analog design by automatically custom sizing an architecture to satisfy specifications for a chosen process over process, voltage and temperature (PVT) variations.? The talk begins with an overview of manual and automated circuit design methods and identifies the iterative and time-intensive steps that result in the analog bottleneck.? We then describe how an equation-based optimizer and optimization friendly process-models are combined with a unified system and circuit formulation that is independent of specification and process to enable analog/RF circuits to be designed and ported efficiently while also documenting the operation of the circuit.? Then, innovations and ease-of-use features that address difficulties associated with traditional equation based optimization methods are presented.? The talk concludes with illustrative applications of commercial equation-based optimization tools in ADC, PLL, RF LCO, opamp, regulator and Serdes designs to highlight how this compelling methodology is leveraged for? process and corner aware, simultaneous optimization of system and circuit across different levels of hierarchy and abstraction.

Webinar: Optimizing Data Analytics for the Smart Grid

by @ 7:22 am. Filed under ALL, Computers/Software, Electrical/Power

THURSDAY October 18, 2012
SPECTRUM Magazine?
Speakers: Eric Nelson, Managing Principal, Synaptitude; Tao Hong, Ph.D., Head of Energy Forecasting, SAS
Time: 11:00 AM (PDT)
Cost: none
Place: on the Web
RSVP: from website

Mtg: Bloom Energy: Reliable Power for Mission Critical Systems

by @ 7:21 am. Filed under ALL, BioEngineering, Computers/Software, Electrical/Power

WEDNESDAY October 17, 2012
SCV Power & Energy and Industry Applications
Speaker: to be announced
Time: Networking & diner at 6:00 PM, Presentation at 7:00 PM
Cost: $30.00 for IEEE members, $40.00 non-members, $15.00 Student IEEE members ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Road (101 at Montegue Expy), Santa Clara
RSVP: from website

Mtg: FPGA-Enabled Power Electronics Systems, Past to Present

by @ 7:17 am. Filed under ALL, Electrical/Power, Electronics Design, Engineering Mgmt

WEDNESDAY October 17, 2012
SCV Power Electronics Chapter
Speaker: James Bonanno, consultant
Time: Networking & Pizza at 6:00 PM, Presentation at 6:30 PM
Cost: Donations for food accepted
Place: Texas Instruments, Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

The ubiquitous DSP microcontroller is a long standing aspect of digital control for power electronics and drive systems.? During the last ten years, the emergence of the FPGA as a central feature in digital controls for power electronics has emerged, and in many cases is becoming the main component in digital control architecture.? The advantages of deterministic loop timing, parallel processing, flexible design tools, and relatively low cost for high density devices are real.? These features make the use of FPGA technology quite attractive for many applications.? Particularly as the number of topologies in the application of power electronics proliferates, FPGAâ??s are well suited to the performance demands.? Such applications may include multi-level converters, power factor correction, and alternative energy.? This talk will feature some historical perspectives on FPGA use in power electronics, with specific industrial examples, and then migrate into present state of the art.? Current applications are highlighted, then some time will be spent talking about the tools and techniques for FPGA based controllers.? This includes the use of higher level languages for systematic generation of HDL firmware.? The talk concludes with perspectives on the future of FPGA based power electronic systems.

Mtg: Wearable Robots for Today and Tomorrow

by @ 7:16 am. Filed under ALL, BioEngineering, Computers/Software, Electronics Design, Engineering Mgmt

WEDNESDAY October 17, 2012
SCV Engineering in Medicine and Biology Chapter
Speaker: Russ Angold, Co-Founder and CTO, Ekso Bionics
Time: Optional dinner, 6:15 PM, Stanford Hospital Cafeteria. Meeting at 7:30 PM
Cost: none (for meeting)
Place: Room M-114, Stanford University Medical School, Stanford
RSVP: not required

Mtg: California Road Map for Commercial Rollout of Fuel Cell Electric Vehicles: Hydrogen Infrastructure Opportunities

by @ 7:14 am. Filed under ALL, Electrical/Power, Electronics Design

WEDNESDAY October 17, 2012
SCV Vehicular Technology Chapter
Speakers: Nico Bouwkamp and Bill Elrick, California Fuel Cell Partnership (CaFCP)
Time: Light lunch & networking at 11:30 AM; presentation at 12:00 Noon
Cost: none for IEEE members; $5 for others.
Place: Cadence Corporation., Bldg. 10 Auditorium, 2655 Seely Ave., San Jose
RSVP: not required

Mtg: Software-Defined Networking (SDN): Unleashing the Power of the Network

by @ 7:13 am. Filed under ALL, Communications, Computers/Software, Engineering Mgmt

TUESDAY October 16, 2012
SCV Consultants’ Network of Silicon Valley
Speaker: Robert Keahey, SummaLogic LLC
Time: 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required

Mtg: Novel Thermal Interface Materials for 3D Chip Stacks

by @ 7:12 am. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors

TUESDAY October 16, 2012
SCV Nanotechnology Chapter
Speaker: Srilakshmi Lingamneni, Ph.D Candidate, Stanford Nanoheat Laboratory, Stanford University
Time: 12:00 PM Noon
Cost: IEEE Members: $5; Non-IEEE Members: $10 (Light lunch of pizza and drinks provided)
Place: TI Auditorium E-1, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

This talk will present an overview of the broad spectrum of research work being carried out at the Stanford Nanoheat Laboratory, the state of the art thermal characterization tools at our lab and the novel mechanical characterization tools that are being developed.? It will discuss in detail the past work, latest developments and future directions of research in nanostructured interface materials.? The talk will then explore the thermal challenges of 3D IC integration and new material requirements for thermal management in 3D packaging and discuss the novel interface materials that are being developed.

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