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December 11, 2012

Mtg: New Wafer-Level Embedded Package Structure and Technology using Large-Scale Panel Assembly

by @ 5:16 pm. Filed under ALL, Electronics Design, Semiconductors
 

THURSDAY February 21, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Akio Katsumata, General Manager, J-Devices Corporation
Time: Registration at 11:30 AM; Buffet lunch at 11:45; Presentation at 12:15 PM
Cost: $15 for lunch ($5 for students, unemployed); no cost for presentation
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv

This presentation describes a new embedded package structure and technology for the next generation of WLP, the Wafer level Fan-Out Package – WFOPâ?¢.? A face-down mounting style, the WFOP has a metal stainless steel or copper plate as a basis for the redistribution interconnection (more…)

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