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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

June 29, 2013

Mtg: Memristive Devices for Computing

by @ 8:28 am. Filed under ALL, Computers/Software, NanoEngineering, Semiconductors
 

TUESDAY July 9, 2013
SCV Electron Devices Chapter
Speaker: Dr. J. Joshua Yang, Hewlett Packard Laboratories
Time: Networking and pizza at 6:00 PM; Presentation at 6:15 PM
Cost: None
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information and offer several (more…)

June 26, 2013

Flash Memory Summit

by @ 7:13 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

8th Annual Flash Memory Summit
– August 13-15, 2013   – Santa Clara Convention Center
– Tutorials   – Exhibits   – Keynotes   – Sessions
This power-packed 3-day event covers the latest topics in flash memory — flash in embedded systems, laptop/tablet design, flash in enterprise storage systems, green flash, solid state drives, flash performance, flash-based design, flash in computers, mobile applications, software, new non-volatile memory technologies, reliability, security, and much more!
Pre-conference Seminars and Tutorials:   – Intro to SSDs   – Intro to NVM Express   – Creating Storage-Class Persistent Memory   – Universal Flash Storage … and more.
Save $100 – use Priority Code “IEEE”.   Earlybird rates through August 11th.   Visit the website: www.flashmemorysummit.com

Mtg: Low-Power Design Essentials

by @ 7:11 am. Filed under ALL, Electronics Design, Semiconductors
 

IEEE-SCV-PACE Evening Short Course
Low-Power Design Essentials
– Monday, July 15, 2013     – Maxim, San Jose
This 3-hour short course presents an overview of the basics and advanced techniques in low-power design: fundamentals of low-power design and well-established techniques; recent trends and applications;techniques to reduce energy even more aggressively over the next decade. For full information, visit the website: pace-course2013.eventbrite.com

Conf on Packaging and Integration of Electronic and Photonic MicroSystems

by @ 7:09 am. Filed under ALL, Electronics Design, Semiconductors
 

ASME InterPACK 2013
Conference and Exhibition on Packaging and Integration of Electronic and Photonic MicroSystems
– July 16-18, 2013     – Hyatt Regency, San Francisco Airport
Focus of InterPACK:   � Advanced Packaging   � Electro-Thermal-Mechanical Issues in Packaging (Multi-Physics)   � Materials and Processes   � MEMS and MEMS Packaging   � Manufacturing and Test   � Modeling and Simulation   � Nanotechnology and NEMS   � Photonics and Optics   � Reliability   � Thermal Management   � Emerging Technologies
IEEE Members get the ASME rates.   For full information, visit the website: www.asmeconferences.org/InterPACK13

Besser Associates Summer/Fall Classes (RF, Wireless)

by @ 7:03 am. Filed under ALL, Communications, Electronics Design
 

The worldwide leader in RF and Wireless Training
Besser Associates Summer/Fall Classes
Headquartered in Mountain View since 1985, we have delivered theory with hands-on practical training to professionals working with analog, RF, wireless, digital, and networking technologies — to over 45,000 people. Get more information on these upcoming local courses:
Applied RF Techniques I (Aug 12-Aug 16)   –DSP: Understanding Digital Signal Processing (Aug 12-Aug 14)   –Practical Digital Wireless Signals: Measurements and Characteristics (Aug 12-Aug 16)   –Behavioural Modeling & Digital Pre-Distortion of RF Power Amplifiers (Aug 12-Aug 14)   –Intro to Data Converters (Aug 15-Aug 16)   –Power Conversion & Regulation Circuits for VLSI Systems (Aug 19-Aug 22)
For these and other classes, or customized/private courses at your facility, download our Schedule/Flyer (PDF) or visit the website: www.besserassociates.com

Position: Program Director of Engineering & Technology

by @ 7:02 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

UC Berkeley Extension POSITION ANNOUNCEMENT
Program Director of Engineering & Technology
— Salary: $65,736 – $79,176     — Closing Date: July 8, 2013
UC Berkeley Extension’s Dept. of Engineering and Technology manages courses, contracts and curricula serving 2300 enrollments in 200 programs/courses. You will provide academic leadership and fiscal management, be responsible for academic quality, develop new courses and curricula, and do strategic planning.   Requires a graduate degree in Engineering, Information Systems or Technology or the equivalent; at least 3 years of recent experience; excellent organizational skills; and ability to form successful relations with instructors.
For full details and submission information, download our description: extension.berkeley.edu/work/pdf/ce2-ET.pdf (PDF).

PICMET/SV: Management of Engineering and Technology

by @ 7:01 am. Filed under ALL, Engineering Mgmt
 

Theme: “Technology Management in the IT-Driven Services”
PICMET/SV: Management of Engineering and Technology
— July 28 – Aug 1, 2013     — Marriott Hotel, San Jose
This high-impact conference sets the stage for technology management for decades to come.
Short Courses:   – Organizational Project Management in Practice   – New Trends and Practices in Silicon Valley’s Innovation System   – A Brief Introduction to Social Network Analyses, with Examples in the Study of Innovation   – Entrepreneurship and Innovation: Some Basic Concepts   – Global Business Incubation and Development for Technology Startups   – Total System Innovation Management
Plus 9 Keynote speakers, sessions, panels, social events.   Discount of 20% for 5 or more;   IEEE Members save $300.   Visit our website for details: www.picmet.org

June 25, 2013

Mtg: Magneto-Optic Analysis of Magnetic Microstructures

by @ 3:07 pm. Filed under ALL, NanoEngineering, Optics/Displays
 

WEDNESDAY June 26, 2013
OEB Magnetics Chapter
Speaker: Rudolf Schaefer, Leibniz Institute for Solid State and Materials Research (IFW), Dresden, Germany
Time: 3:00 PM
Cost: none
Place: Lawrence Berkeley National Labs
RSVP: required, by email, to Peter Fischer, peter.fischer@ieee.org at least two days prior to the meeting.
Web: ewh.ieee.org/r6/oeb/mag

The rich world of magnetic microstructure or magnetic domains, extending from visible dimensions down to the nano-scale, forms the mesoscopic link between the fundamental physical properties of a magnetic material and (more…)

Tutorial on LDPC Decoding, VLSI Architectures and Implementations

by @ 2:45 pm. Filed under ALL, Communications, Electronics Design, Semiconductors
 

WEDNESDAY August 14, 2013
SCV PACE (Professional Activities Committee for Engineers)
Speakers: Dr. Ned Varnica, Marvell Semiconductor; Dr. Kiran Gunnam, NVIDIA
Time: 7:00 PM to 9:30 PM
Cost: $30
Place: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara
RSVP: from website
Web: ldcp-fms-2013.eventbrite.com

LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD.  Tutorialâ??s target audience is system engineers and (more…)

Mtg: BRIC: Overview of the Emerging Markets

by @ 2:19 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt
 

TUESDAY September 10, 2013
SCV Electromagnetic Compatibility Chapter
Speaker: Mark Maynard, SIEMIC, Inc.
Time: Networking/light dinner at 5:30 PM; Presentation at 6:30 PM
Cost: none
Place: Agilent Technologies, 5301 Stevens Creek Blvd., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/emc

The growing markets in Brazil, Russia, India and China (BRIC) now are responsible for a sizable portion of the profits for most global companies.  Working against this prize is a formidable maze of culture, laws, and overlapping (more…)

Mtg: Earthquake Hazards in the San Francisco Bay Region

by @ 2:07 pm. Filed under ALL, Electrical/Power, Electronics Design
 

TUESDAY September 3, 2013
SCV Consultants’ Network of Silicon Valley
Speaker: Kent Fogleman, USGS National Strong-Motion Project
Time: Presentation at 7:00 PM
Cost: none
Place: Agilent Technologies, 5301 Stevens Creek Blvd., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

Most people who live in the San Francisco Bay Region know about the magnitude (Mw) 7.8 1906 San Francisco earthquake (“The Big One”), but many other Bay Area faults are also hazardous.  This talk will discuss the (more…)

Mtg: “Pebble” the Smartwatch

by @ 1:18 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY July 23, 2013
SCV Consumer Electronics
Subject:
Speaker: Eric Migicovsky, Founder, Pebble Technology
Time: Networking at 6:30 PM; Presentation at 7:00 PM
Cost: IEEE Members: $5; non-members: $10 (no charge for students)
Place: Microsoft, 1085 La Avenida St., Mountain View
RSVP: from website
Web: ewh.ieee.org/r6/scv/ce

Wearable computing is the next exciting market after the success of smartphones and tablets.  Pebble is designed to be customizable, with downloadable watchfaces and useful internet-connected apps.  Pebble connects to (more…)

June 19, 2013

Mtg: Electrical Signaling at 64Gb/s/Lane

by @ 8:29 am. Filed under ALL, Communications, Electronics Design, Semiconductors
 

THURSDAY June 20, 2013
SCV Solid State Circuits Chapter
Speaker: Dr. Elad Alon, UC Berkeley
Time: Networking and snacks at 6:00 PM; Presentation at 6:30 PM.
Cost: none
Place: Texas Instruments Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: from website
Web: sites.ieee.org/scv-sscs

The demand for I/O bandwidth in modern SoCs continues to grow at an exponential rate, forcing the per-lane bandwidth of electrical links to rise at a tremendous pace.  While there have been several demonstrations of electrical I/O operating (more…)

June 13, 2013

Mtg: What Every Electrical Engineer Should Know about Nonlinear Circuits and Systems

by @ 8:24 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY July 10, 2013
SCV Circuits and Systems Chapter
Speaker: Prof. Michael Peter Kennedy, CAS Distinguished Lecturer, University College Cork, Ireland
Time: Networking/Light Dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation for food
Place: QualComm, Building B, 3165 Kifer Road, Santa Clara
RSVP: from website
Web: sites.ieee.org/scv-cas

The theory of Circuits and Systems lies at the core of Electrical & Electronic Engineering education. Traditionally, training in circuits and systems has emphasized linear concepts and has focused almost exclusively on linear analysis and synthesis (more…)

Mtg: Splitting One Photon to Two Electrons: Toward Breaking the Single Junction Efficiency Limit

by @ 8:06 pm. Filed under ALL, Electrical/Power, Electronics Design, Optics/Displays, Semiconductors
 

TUESDAY July 9, 2013
SCV Nanotechnology Chapter
Speaker: Dr. Jiye Lee, Postdoctoral fellow, Molecular Foundry, LBNL
Time: Registration & pizza at 11:30 AM; Presentations at 12:00 PM Noon
Cost: IEEE Members: $5, Non-members: $10
Place: Texas Instruments (TI) Auditorium E-1, 2900 Semiconductor Drive, Santa Clara
RSVP: from website
Web: sites.ieee.org/sfbanano

Conventional solar cells generate one electron for each absorbed photon.  Any excess photon energy above the bandgap is wasted as heat.  This fundamental energy loss imposes the Shockley-Queisser limit of 34% for single optimized semiconductor junction.  Singlet (more…)

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