IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

July 29, 2013

Mtg: Advanced Spintronic Materials for Generation and Control of Spin Current

by @ 1:18 pm. Filed under ALL, NanoEngineering, Optics/Displays, Semiconductors

TUESDAY September 17, 2013
SCV Magnetics Chapter
Speaker: Dr. Koki Takanashi, IEEE Distinguished Lecturer, Institute for Materials Research (IMR), Tohoku University
Time: Networking and pizza at 6:45 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required

â??Spin currentâ? — i.e., the flow of spin angular momentum — in magnetic nanostructures has emerged as a fascinating physical concept during the recent development of spintronics.  In magnetic nanostructures, magnetism correlates (more…)

Big Data TechCon 2013

by @ 12:43 pm. Filed under ALL, Computers/Software, Engineering Mgmt

Big Data TechCon 2013
– October 15-17, 2013   – Hyatt Regency, Burlingame
– Tutorials, Technical Classes   – Keynotes, Exhibits, more
Practical, how-to classes and tutorials for IT and Big Data professionals: Hadoop, Map/Reduce, R, Hive, Pig, NoSQL, Mongo DB, Cassandra.   Learn how to   – Collect, sort and store   – Structured and unstructured data   – Process real-time data   – Master Big Data tools and technologies   – Integrate data collection technologies with data analytics   Tutorials:   – Hadoop: A One-Day, Hands-On   – Approach to Big Data Solutions   – Getting Started with Cassandra   – Storing and Analyzing Your Data with Apache Hive … and more.
Register by August 2nd, to save $400. Add’l $100 with code “IEEE“.   For full details, see

Mtg: Semiconducting Nanowire Arrays Grown Directly on Graphene: Towards Precision Placement of Wafer Scale Nanowire Arrays with Improved Electrical Contact for Energy Storage and Harvesting

by @ 12:00 pm. Filed under ALL, Electrical/Power, NanoEngineering, Semiconductors

WEDNESDAY September 11, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: John Alper, PhD Candidate, UC-Berkeley
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20; $10 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website

Semiconducting nanowires (NWs) have been demonstrated as promising in a number of devices due to novel properties which are intrinsic to their nanoscale. Silicon NW geometry allows for relaxation of mechanical stress associated with lithium insertion, potentially avoiding the rapid degradation (more…)

Mtg: Circuits and Systems for Wearable and Implantable Medical Devices

by @ 10:43 am. Filed under ALL, BioEngineering, Electronics Design, Semiconductors

MONDAY September 16, 2013
SCV Circuits and Systems Chapter
Speaker: Prof. Wouter A. Serdijn, CAS Distinguished Lecturer, Head Biomedical Electronics Laboratory, Delft University of Technology, The Netherlands
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 requested for food
Place: QualComm, Building B, 3165 Kifer Road, Santa Clara
RSVP: from website

In the design process of wearable and implantable medical devices (IMDs), such as hearing instruments, pacemakers, cochlear implants and neurostimulators, the tradeoff between performance and power consumption is (more…)

Mtg: UWB Technology Development and Applications in Japan

by @ 10:24 am. Filed under ALL, Communications, Electronics Design, Semiconductors

MONDAY August 5, 2013
SCV Microwave Theory and Techniques Chapter
Speaker: Hisashi Nishikawa, Director of Development, GIT Japan Inc.
Time: 6:30 PM
Cost: none
Place: Agilent Technologies, 5301 Stevens Creek Blvd, Santa Clara
RSVP: not requred

Ultra-Wideband (UWB) wireless technologies that consist of RF and Baseband chips with a dedicated wideband antenna will be presented, with examples of using UWB technology for high-speed data transmission, high-precision distance (more…)

Mtg: PG&E 500 kV Series-Compensated Transmission Line Relay Replacement: Design Requirements and Testing

by @ 10:03 am. Filed under ALL, Electrical/Power

THURSDAY August 22, 2013
SF Power & Energy Chapter
Speaker: Davis Erwin, PE, System Protection, Pacific Gas & Electric Company
Time: Networking and light lunch at 11:30 AM; Presentation at 12:00 Noon
Cost: none, for IEEE Members; $5 for Non-members
Place: Pacific Gas & Electric, Room #305, 77 Beale Street, San Francisco
RSVP: by August 20 to Charles Mee,, 415-703-1147

Pacific Gas and Electric Company (PG&E) owns an extensive 500 kV series-compensated transmission line network.  The availability of this network is critical to serving Northern California loads and regional power (more…)

Mtg: Introducing ComponentCostEstimator (CCE) – A Game-Changing Power Tool from Lytica

by @ 9:38 am. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors

TUESDAY August 27, 2013
SCV Consumer Electronics Chapter
Speaker: Ken Bradley, President & Founder, Lytica Inc
Time: Networking and food at 6:30 PM; Presentation at 7:00 PM
Cost: none for IEEE members; $10 for non-members
Place: NVIDIA, Building E, Marco Polo Room, 2800 Scott Blvd, Santa Clara
RSVP: from website

Doing more with less was the design spec for ComponentCostEstimator.  Leveraging the statistical models within the worldâ??s largest independent database of â??Real-Worldâ?? pricing of Electronic Components, CCE augments (more…)

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