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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

November 18, 2013

3D Architectures for Semiconductor Integration & Packaging

by @ 9:40 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

Technology for Emerging Device and Systems Integration & Interconnect
3D Architectures for Semiconductor Integration & Packaging     – December 11-13, 2013   – Hyatt Regency SFO, Burlingame
3-D integration and packaging represents a paradigm shift for the semiconductor industry, opening entirely new pathways for performance advancement and new prospects for industry growth.     Focus:   – Market Impacts and Analysis   – End-user Perspectives   – 3-D Integration & Packaging Technologies   – Design Methodology and Tools   – Mfg Issues and Solutions     Sessions on:   – Emerging Pathways in Heterogeneous 3D   – Options for Memory-Logic Integration   – Interposers   – Thermal Challenges, Solutions, Impact   – Thin Wafer Handling and Direct Bonding   – Advances in 2.5D/3D Design and Test   … and more.
Reduced Fees through October 31 — save $150.   Visit techventure.rti.org .

20131211all

Mtg: Remote Ground Fault Protection Issues

by @ 9:26 am. Filed under ALL, Electrical/Power
 

TUESDAY November 19, 2013
SF Industry Applications Chapter
Speaker: Sergio Panetta, Vice President of Engineering, I-Gard Corporation
Time: Networking and relaxation at 5:30 PM, Presentation at 6:00 PM, Dinner at 7:00 PM
Cost: $25 ($10 for IEEE Student members)
Place: Sinbad’s Restaurant, Pier 2 The Embarcadero, San Francisco
RSVP: Please email Byron Lee, byee@yeiengineers.com for reservations and to qualify for the drawing
Web: www.e-grid.net/docs/1311-sf-ias.pdf

Power continuity is essential in wind power projects where a trip-out due to ground fault can have serious economic or operational consequences.  An arcing phase-to-ground fault can totally destroy the equipment.  Consequential downtime adds to (more…)

20131119scv

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