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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 24, 2014

Mtg: 3D Gesture Recognition: A 512×424 CMOS 3D Time-of-Flight Image Sensor with Photo-Demodulation; Ultrasonic 3D Rangefinder on a Chip

by @ 4:12 pm. Filed under ALL, Electronics Design, Optics/Displays, Semiconductors

MONDAY April 21, 2014
SCV Circuits and Systems Chapter, with Solid State Circuits
– signal path, frames, range error; MEMS, ASIC …
Speakers: Dr. Cyrus Bamji, Microsoft Corp.; Dr. Richard Przybyla, Chirp Microsystems
Time: Networking/Light Dinner at 6:30 PM; Presentations at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm, Building B, 3165 Kifer Road, Santa Clara
RSVP: from website

In the first talk, the pixel and signal path of a 512Ã?424-pixel ToF image sensor is presented.  Consecutive frames with different modulation frequencies are combined, which enables a range error of less than 1% over ranges from 0.8 to 4.2m.  Modulation (more…)


Mtg: Bayesian Methods for Sparse Signal Recovery

by @ 3:37 pm. Filed under ALL, Communications

WEDNESDAY May 21, 2014
OEB Signal Processing Chapter
– compressive sensing, signal recovery, re-weighted methods …
Speaker: Bhaskar D. Rao, University of California at San Diego, SPS Distinguished Lecturer
Time: 6:00 PM
Cost: $20 for IEEE members; $25 for non-members
Place: Zephyr Grill, 1736 First St., Livermore
RSVP: from website

Compressive sensing (CS) as an approach for data acquisition has recently received much attention. In CS, the signal recovery problem from the observed data requires the solution of a sparse vector from an underdetermined system of equations.  The underlying (more…)


2014 Signal and Image Sciences Workshop

by @ 3:29 pm. Filed under ALL, Communications, Computers/Software

WEDNESDAY May 21, 2014
OEB Signal Processing Chapter
– 1-day: video processing, machine learning, pattern analysis …
Speakers: Dr. Pietro Perona, Caltech; and others
Time: 8:00 AM – 5:00 PM
Cost: none (includes lunch) – requires identification (Driver’s license, passport, etc) for admission to the venue
Place: Livermore Valley Open Campus, HPC Innovation Ctr., Lawrence Livermore National Laboratory, Livermore
RSVP: from website


Mtg: System Level On-Chip ESD Protection

by @ 2:52 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors

THURSDAY April 15, 2014
SCV Electron Devices Chapter
– high current, parasitics, waveforms, latchup, tests …
Speaker: Dr. Vladislav Vashchenko, Maxim Integrated Corp.
Time: Networking and pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
RSVP: not required

A significant paradigm shift in systems and analog IC design has been initiated by new market demands over last decade.  Integration of emerging technologies, increases in data rate, rapid evolution of portable and mobile devices, lower power consumption and (more…)


Mtg: Information Flow in Wireless Networks: Similarity to Water in Pipes

by @ 9:51 am. Filed under ALL, Communications

WEDNESDAY April 23, 2014
SCV Information Theory Chapter
– modeling, max-flow, min-cut, compress-and-forward …
Speaker: Adnan Raja, Ph.D., Fastback Networks
Time: Food and drinks at 5:30 PM; Presentation at 6:00 PM
Cost: none; free parking after 4 PM
Place: Room 202, Packard Bldg, Stanford University, Stanford
RSVP: not required

A wired network is modeled as a flow network, which is a directed graph where each edge has a capacity and the flow on each edge cannot exceed the capacity.  This is similar to a commodity network, like traffic in a road system or fluid in pipes. The very (more…)


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