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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

July 31, 2015

Employment at the Electrical Engineering Department at Sonoma State University

by @ 7:29 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power, Electronics Design, Optics/Displays, Signal Processing
 


SSU logoThe Electrical Engineering Department at Sonoma State University invites qualified candidates to apply for the part-time instructor position to teach the related topics, including: Programing and Modeling, VHDL, Digital Signal Processing, RF & Wireless, Fiber Optics Communications.

In addition, the following teaching positions are immediately available for Fall 2015:
ES 220: Electronics II (4) / Lecture: T & TH: 1-2:15 pm Lecture / Lab W: 1-3:45 pm
ES 400: Linear System Theory (3) / Lecture: Mon & Wed 4:00-5:15 pm 
ES 210: Digital Circuit & Logic Design (4) – Lecture: Mon & Wed 1:00-2:15 / Lab: 2:15-5:00 pm
ES 112: Fundamentals of Digital Logic Design (1) – Lab Only: Tuesday 9:00-11:45 am

The expected starting date for the above courses is August 24, 2015. More information about the courses can be found here:http://www.sonoma.edu/engineering/courses.html. The Fall class schedule is available here:http://www.sonoma.edu/engineering/schedules/schedule_fa2015.pdf.

Required qualifications: Ph.D. in relevant areas of specialties or Master’s degree with extensive industry experience. The part-time instructor position is a paid position. For more information please contact: farid.farahmand@sonoma.edu.

Sonoma State University is 50 minutes north of the Golden Gate Bridge and is one of 23 campuses in the California State University system.

 

20150801ALL

23rd International Symposium on High Performance Interconnects

by @ 7:27 pm. Filed under ALL, Electrical/Power, Electronics Design, Semiconductors
 

 23rd International Symposium on High Performance Interconnects

The IEEE HOT INTERCONNECTS 23 Conference on August 26-28 features state- of-the-art hardware and software architectures and implementations for interconnection networks of all scales, ranging from multi-core on-chip networks to those within systems, clusters, data centers, and clouds. See the complete Advance Program for conference, tutorials and keynotes. The conference and tutorials are discounted for Registration before August 14.
* Host Keynote: Commercial Computing Trends and Their Impact on Interconnect Technology – Rick Hetherington, Oracle
* Keynote 2: Recent Advances in Machine Learning and Their Application to Networking – David Meyer, Brocade
* Invited Paper: Intel Omni-Path Architecture: Enabling Scalable-, High-Performance Fabrics – Todd Rimmer, Intel; * Panel: HPC vs. Data Center Networks; Regular Sessions: * Network and Interface Architectures, * Optics and NOCs, * Efficient Network Design; Tutorials: * Accelerating Big Data Processing with Hadoop, Spark, and Memcached Over High-Performance Interconnects, * ONOS Tutorial Hot Interconnect, * Flow and Congestion Control for High Performance Clouds: How to Design and Tune the Datacenter Fabric & SDN for Big Data, * Software-defined Wide-Area Networking: Challenges, Opportunities and Reality

20150826ALL

July 30, 2015

3D Printed Package Components for High Performance Packaging

by @ 2:14 pm. Filed under ALL, Consumer Electronics, Semiconductors
 

Tuesday, August 25, 2015 
SCV Consumer Electronics (CE) 
Subject: 3D Printed Package Components for High Performance Packaging 
– print complex structures with multi-material inks, mechanics of the technology and manufacturing platform, package types such as SiP, PoP … 
Speaker: Philip Rogren, VP of Product Development, EoPlex 
Time: 6:30 pm: pizza & drinks, 7:00 – 8:30 pm: Presentation 
Cost: IEEE members – $5, Non-IEEE members – $10, IEEE CES and IEEE Student members – Free 
Location: NVIDIA – 2800 Scott Blvd., Building E, Santa Clara 
Event Details: https://www.eventbrite.com/e/ieee-consumer-electronics-society-aug-25-2015-3d-printed-package-components-for-high-performance-tickets-17963994792

20150825ALL

Gathering Light

by @ 1:39 pm. Filed under ALL, Signal Processing
 

Thursday, October 15, 2015 
SCV Signal Processing Society (SPS)
Subject: Gathering Light 
– prime lenses that provide an optical zoom, small mirrors allow reconfiguring the cameras to select.., architecture of this flexible computational camera… 
Speaker: Dr. Kari Pulli, VP of Computational Imaging, Light 
Time: 6:30 pm: Networking/Light Dinner; 7:00 pm: Announcements; 7:05 to 8:15 pm: Presentation 
Cost: Free 
Location: AMD Commons C-6/7/8, 991 Stewart Dr., Sunnyvale 
Event Details: http://www.ewh.ieee.org/r6/scv/sps/20151015Abstract.html 

20151015ALL

Understanding an Industry Technical Staff Pipeline

by @ 1:20 pm. Filed under ALL, Engineering Mgmt
 

Thursday, August 13, 2015 
SCV Technology and Engineering Management Society (TEMS) 
Subject: Understanding an Industry Technical Staff Pipeline 
– how the corporate staffing system works, criteria are used for career advancement…
Speaker: Dr. Michael Condry, Former Chief Technical Officer, Intel Corp. 
Time: 8:00 â?? 9:00 AM (PDT) 
Cost: Free 
Location: Webinar 
Event Details: https://lnkd.in/ejsU7je

20150813ALL

July 28, 2015

Packaging Solutions and Innovations with Compression Molding

by @ 4:02 pm. Filed under ALL, Semiconductors
 

Thursday, August 27, 2015 
SCV Components, Packaging, and Manufacturing Technologies (CPMT) 
Subject: Packaging Solutions and Innovations with Compression Molding 
– large-area-size substrates, limited by current transfer mold, slow “dipping” of the devices into either a melted granular or liquid mold compound …
Speaker: C. H. Ang, Senior Technical Support Manager, TOWA, USA 
Time: 11:30 am, check-in, light food, networking; 12 noon: presentation 
Cost: $5 non-IEEE members, Free for members (please use code IEEE2015); Talk-Only: Free 
Talk-Only attendees: please check-in by 11:45 
Location: Texas Instruments, Building E Conference Center, 2900 Semiconductor Dr., Santa Clara 
Event Details: http://www.cpmt.org/scv/meetings/cpmt1508l2.html

20150827ALL

July 27, 2015

Functional Coatings for PV Glass

by @ 4:34 pm. Filed under ALL, Optics/Displays
 

Wednesday, August 12, 2015 
SCV PhotoVoltaic (PV) 
Subject: Functional Coatings for PV Glass 
– very low-cost anti-reflective coatings, engineered to survive high temperatures, humidity, abrasion, soiling …
Speaker: Brenor Trophy, CTO and VP Business Development, Enki Technology
Time: 6:30 pm, check-in, light food, networking; 7:00 to 8:30 pm: presentation 
Cost: Free 
Location: Palo Alto Research Center, (G.E. Pake Auditorium), 3333 Coyote Hill Road, Palo Alto 
Event Details: http://ewh.ieee.org/r6/scv/pv/

20150812ALL

2D Crystals for Smart Life

by @ 4:07 pm. Filed under ALL, Communications, Computers/Software, Electrical/Power, Semiconductors, Signal Processing
 

Tuesday, August 11, 2015 
SCV Electron Devices Society (EDS) 
Subject: 2D Crystals for Smart Life 
– 2D crystals for.., green electronics needed to support Big Data, IoT/IoE and social media …
Speaker: Prof. Kaustav Banerjee, University of California, Santa Barbara 
Time: 6 pm: Networking, 6:15 pm: Presentation
Cost: Free 
Location: Texas Instruments, Building E Conference Center, 2900 Semiconductor Dr., Santa Clara 
Event Details and Registration: http://sites.ieee.org/scv-eds/

20150811ALL

July 23, 2015

Electrostatic Functionalization of Carbon Based Nanomaterials and Applications in Chemical, Gas and Bio-Sensing

by @ 6:09 pm. Filed under ALL, Electronics Design, NanoEngineering
 

Tuesday, August 18, 2015 
SF Nanotechnology Council 
Subject: Electrostatic Functionalization of Carbon Based Nanomaterials and Applications in Chemical, Gas and Bio-Sensing 
– electrostatic charging for the functionalization of carbon based nanomaterials, thin films …
Speaker: Dr. Vasuda Bhatia, Professor, Amity Institute 
Time: 11:30: Networking, Pizza & drinks; 12:00 noon to 1 pm: Seminar 
Cost: Free 
Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara 
Event Details and Registration: http://sites.ieee.org/sfbanano/

20150818ALL

July 22, 2015

5G: Expectations and the Road Ahead

by @ 1:54 pm. Filed under ALL, Communications, Electronics Design
 

Wednesday, September 9, 2015 
SCV Communications Society (ComsocSCV) 
Subject: 5G: Expectations and the Road Ahead 
– path to full 5G feature set network, optimized derivative LTE versions for various vertical markets …
Speakers: Francis Chow, VP & GM, Communications Business Unit, Altera; Joe Madden, Principal Analyst, Mobile Experts LLC 
Moderator: Mehran Nekuii, Treasurer, ComsocSCV 
Time: 6:30 pm: Registration, refreshments, and networking; 7 pm: presentation 
Cost: Presentation is free, $5 donation expected for pizza and water 
Location: Texas Instruments (TI), Building E Conference Center, 2900 Semiconductor Dr., Santa Clara 
RSVP: http://bit.ly/1RLKgy3 
Website for more information: www.comsocscv.org

20150909ALL

July 20, 2015

The Future of Energy: Smart Grid and Beyond – Fall Banquet

by @ 5:59 pm. Filed under ALL, Electrical/Power, Signal Processing
 

Wednesday, October 21, 2015 
SF Power and Energy (PES) 
Subject: The Future of Energy: Smart Grid and Beyond 
– Fall Banquet, roadmap, Three key visionary concepts, solar PV, Intelligent Electronic Device (IED) integration… 
Speaker: John D. McDonald, PE Director, Technical Strategy & Policy Development – GE Energy Management 
Time: 5:00 pm: Networking; 6:00 pm: Dinner; 7:00 pm to 9:00 pm: Presentation 
Cost: IEEE members $30, Non-members $40, IEEE Life Members $15, Students $15 with valid Student ID. Cash Bar 
RSVP and payment must be received by October 7 at https://meetings.vtools.ieee.org/m/33899
Location: Jillian’s at Metreon, 175 Fourth Street, San Francisco

20151021ALL

July 17, 2015

Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability

by @ 12:42 pm. Filed under ALL, Electronics Design, Semiconductors, Signal Processing
 

Thursday, August 6, 2015 
SCV Reliability Society and SCV Electron Devices Society 
Subject: Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability 
– shift in MOSFET parameters, defect generation explained from both macroscopic and stochastic viewpoints … 
Speaker: Souvik Mahapatra, Professor of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India 
Time: 6:00 to 6:30 pm: Check-in and refreshments 6:30 to 7:30: Presentation 
Cost: Free 
Location: Qualcomm, 3165 Kifer Rd, Santa Clara, in the cafeteria 
Event Details: http://ieee-scv-rel-aug-2015.eventbrite.com

20150806ALL

July 15, 2015

Two Part Short Course: Evolution of High Speed Analog Front End ICs; Fast and Accurate System Level Simulation of Time-Based Circuits

by @ 4:19 pm. Filed under ALL, Electronics Design, Semiconductors
 

Thursday, August 20, 2015 
SCV Solid State Circuits Society (SSCS) 
Subject: Selected Analog Design Topics a Two Part Short Course: Evolution of High Speed Analog Front End ICs; Fast and Accurate System Level Simulation of Time-Based Circuits 
– Modem for high speed communications, 5um down to 16nm, Time-based circuits, efficient protocol for encoding edge time information… 
Speakers: Dr. B.K. Ahuja, Dr. Mike Perrott 
Time: 4:00 to 8:30 pm 
Cost: IEEE member: $40 ; Non-IEEE member: $50; TI employee: free; Students and unemployed: $20; Maxim Integrated Employees: $25 
Location: Texas Instruments Auditorium, 2900 Semiconductor Dr, Santa Clara 
Event Details: http://sites.ieee.org/scv-sscs/

20150820ALL

July 14, 2015

Robust 3DIC Package Assembly Process Engineering for High Volume Production

by @ 2:52 pm. Filed under ALL, Electrical/Power, Electronics Design, Semiconductors, Signal Processing
 

Wednesday, August 12, 2015 
SCV Components, Packaging, and Manufacturing Technologies (CPMT) 
Subject: Robust 3DIC Package Assembly Process Engineering for High Volume Production 
– FPGA, CoWoS (Chip-On-Wafer-On-Substrate), low power and latency, manufacturing complexity …
Speaker: Inderjit Singh, Xilinx Inc. 
Time: 11:30 am, check-in, light food, networking; 12 noon: presentation 
Cost: $5 non-IEEE members, Free for members (please use code IEEE2015); Talk-Only: Free 
Talk-Only attendees: please check-in by 11:45 
Location: Biltmore Hotel (a change from our usual TI location), 2151 Laurelwood Road (at 101), Santa Clara
Event Details: http://www.cpmt.org/scv/meetings/cpmt1508l.html 
RSVP: http://www.eventbrite.com/e/robust-3d-ic-package-assembly-process-engineering-for-high-volume-production-registration-17421205294

20150812ALL

July 13, 2015

EMPLOYMENT OPPORTUNITY for Electrical Engineer

by @ 6:40 pm. Filed under ALL, Electrical/Power, Electronics Design, Engineering Mgmt
 

EMPLOYMENT OPPORTUNITY
Electrical Designer Engineer for the U.S. Coast Guard’s Civil Engineering Unit (CEU) in Oakland. Electrical Engineer will prepare drawings, technical specifications, cost estimates, perform site visits and develop designs for renovation, restoration and/or construction of modern or historic Coast Guard facilities. Minimum 10 years’ experience in electrical work, to include design and load balance experience. BSEE (or equivalent) and P.E. required. Apply at:http://sev1tech.catsone.com/careers/

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