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October 26, 2015

Chip and IP block-level verification of ESD networks in the ESDi product (with Live Demo)

by @ 2:00 pm. Filed under ALL, Computers/Software, Electronics Design, Semiconductors, Signal Processing
 

Monday, November 16, 2015 
SCV Circuits and Systems Society (CAS) 
Subject: Chip and IP block-level verification of ESD networks in the ESDi product (with Live Demo) 
– ESDi imports the full-chip layout from GDSII, identifies all the IO-pads/bumps, then extracts parasitic interconnect resistances, electro-migration checks… 
Speaker: Dr. Dündar Dumlugöl, CEO, Magwel NV 
Time: 6:30 pm: Networking/Light Dinner; 7:00 pm: Announcement; 7:05 pm: Presentation; 8:15 pm: Adjourn 
Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member 
Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara 
Event Details: http://sites.ieee.org/scv-cas/ 
EventBrite: https://www.eventbrite.com/e/chip-and-ip-block-level-verification-of-esd-networks-in-the-esdi-product-with-live-demo-by-dr-tickets-19067164402 

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