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Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

November 14, 2016

Containers – Why is the Disruption so Fundamental 

by @ 3:38 pm. Filed under ALL, Computers/Software
 

Tuesday, December 6, 2016 
SCV Computer Society 
Subject: Containers – Why is the Disruption so Fundamental 
– Containers, Docker, applications, tectonic shift and the under-currents that are impacting the layers of the infrastructure …
Speaker: Vipin Jain, Founder/Lead, Contiv Project 
Time: 6:30 pm: Networking, registration, refreshments; 7:00 pm: Presentation
Cost: Free
Location: Cadence, Bldg 10, 2655 Seely Ave., San Jose 
Event Details: http://computer.ieeesiliconvalley.org/ 

20161206ALL

Hyperscale Data Center with Software Defined Infrastructure (SDI) and Rack Scale Design (RSD) for Hyper Cloud 

by @ 3:29 pm. Filed under ALL, Computers/Software
 

Tuesday, November 15, 2016 
SCV Computer Society 
Subject: Hyperscale Data Center with Software Defined Infrastructure (SDI) and Rack Scale Design (RSD) for Hyper Cloud 
– multi-cloud requirements and management of these servers have become more complex to support different types of cloud workloads, Rack Scale Computing, Software Defined Infrastructure …
Speaker: Fulcan Fong, Sr. Cloud Solutions Manager, Intel 
Time: 6:30 pm: Networking, registration, refreshments; 7:00 pm: Presentation
Cost: Free
Location: Cadence, Bldg 10, 2655 Seely Ave., San Jose 
Event Details: http://computer.ieeesiliconvalley.org/ 

20161115ALL

On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and Future

by @ 1:23 pm. Filed under ALL, Computers/Software, Electronics Design, Reliability, Semiconductors
 

Thursday, December 1, 2016 
SCV-SF Electron Device Society (EDS) 
Subject: On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and Future
– ESD protection, killing factor to the time to market of new IC products, ESD protection basics and traditional ESD protection solutions, new CAD tool for full-chip ESD protection circuit design verification… 
Speaker: Prof. Albert Wang, Dept. of Electrical and Computer Engineering, University of California, Riverside 
Time: 6:00 pm: Registration, networking, and refreshments; 6:15 pm to 7:00 pm: Presentation
Cost: Free 
Location: Texas Instruments, 2900 Semiconductor Way, Bldg. E Auditorium, Santa Clara 
Event Details: http://sites.ieee.org/scv-eds/ 

20161201ALL

Wafer Level Process Formation of a Polymer Isolated Chip Scale Package 

by @ 1:03 pm. Filed under ALL, Semiconductors
 

Tuesday, November 22, 2016 
SCV Components, Packaging, and Manufacturing Technologies (CPMT) 
Subject: Wafer Level Process Formation of a Polymer Isolated Chip Scale Package 
– After reflow, this excess solder may cause a high leakage path or short, silicon sidewalls and backside are completely covered by a thin non-conducting polymer material, polymer isolated CSP solution… 
Speaker: Harry Gee, Device Engineer, On Semiconductor 
Time: 11:30 am: Registration, networking, sandwiches/drinks; 12:00 pm: Presentation. Presentation-only: please arrive at 11:45 am to register in advance of beginning of talk. Cost: IEEE Member, students, unemployed: $5; non-IEEE Member: $10; 
Location: Texas Instruments, 2900 Semiconductor Way, Bldg. E Auditorium, Santa Clara 
– Event Details: http://www.cpmt.org/scv/ 

20161122ALL

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