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July 22, 2009

Mtg: Nanopackaging: Nanotechnologies in Microelectronics Packaging

by @ 10:29 am. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Optics/Displays, Semiconductors

WEDNESDAY November 11, 2009
SCV Components, Packaging and Manufacturing Technology Chapter?
Speaker: James E. Morris, Department of Electrical & Computer Engineering, Portland State University, and CPMT Society Distinguished Lecturer
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by Nov 9; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website

While the electronics industry continues to look for the next nanoscale device to take over from the MOSFET, other nanotechnologies are already being developed for microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes (CNTs.)? Composite materials are applicable to all the passive components, (high-k dielectrics, cermet resistors, inductors, and antennas), electromagnetic interference shielding, electrically conductive adhesives, dispensable conductive interconnect “inks,” underfill fillers, and solder enhancement. CNTs find a similar range of applications within composites, but also as thermal and electrical interfaces.? There are other nanoscale structures with great packaging potential, and all of these technologies offer new challenges for effective computer modeling, while new nanoscale modeling techniques provide the tools to understand old effects in new ways.? Little work seems to be going on, however, on the packaging requirements of the nanoelectronics technologies of the future.

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