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September 24, 2009

Mtg: Nehalem-EX: A 45nm, 8-core Enterprise Processor

by @ 2:30 pm. Filed under ALL, Computers/Software, Electronics Design, Semiconductors

THURSDAY October 15, 2009
SCV Solid State Circuits Chapter
Speaker: Stefan Rusu, Senior Principal Engineer, Intel’s Enterprise Microprocessor Group
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building E Auditorium, 2900 Semiconductor Dr, Santa Clara
RSVP: not required

This talk describes a 2.3B transistor, 8-core, 16-thread 64-bit Xeon® EX processor with an on-die 24MB shared L3 cache.? The processor is implemented in a 45nm, 9-metal high-K metal gate process.? Multiple clock and voltage domains are used to reduce power consumption.? Long channel devices and cache sleep mode are used to minimize leakage.? Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die.? The disabled blocks are both clock and power gated to minimize their power consumption.? Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.? The point-to-point I/O links are operating at 6.4GT/s and achieve 25.6GB/s per port.

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