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September 28, 2009

Mtg: Reverse Engineering in the Semiconductor Industry

by @ 4:29 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY November 16, 2009
SCV Circuits and Systems Chapter
Speaker: Randy Torrance, Chipworks
Time: Networking/Pizza at 6:30 PM, Presentation at 7:00 PM
Cost: $2 donation for food
Place: Cadence Design Systems, Building 5, 2655 Seely Avenue, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas (scroll down)

The continuous drive of Moore’s law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns and demanding the adoption of new and more sophisticated technology to analyze chips.? The following types of analysis will be covered in detail:
â?¢ product teardown;
â?¢ techniques used for system-level analysis, both hardware and software;
â?¢ circuit extraction, taking the chip down to the transistor level and working back up through the interconnects to create schematics;
â?¢ process analysis, looking at how the chip is made, and what it is made of.
This presentation is an update of the invited paper given at the 2007 IEEE Custom Integrated Circuits Conference (CICC) with more focus on circuit extraction and cross-referencing between circuit schematics and the 1000’s of physical layout images obtained through generating a mosaic of scanning electron microscopy across all device layers.

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