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October 23, 2009

Mtg: Cost-Effective Low-Power IP Designs for Mobile Communications

by @ 8:13 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY December 10, 2009
SCV Circuits and Systems Chapter
Speaker: Prof. Myung H. Sunwoo, Ajou University, Suwon, Korea
Time: Networking/Pizza at 6:30 PM, Presentation at 7:00 PM
Cost: $2 donation for food
Place: Cadence Design Systems, Building 5, 2655 Seely Avenue, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas

The talk presents four low-power high-speed SOC IP designs for communication systems.? First, a new continuous flow mixed-radix (CFMR) FFT processor is presented, which uses the mixed-radix (radix-4/2) algorithm and an in-place memory strategy to reduce area.? CFMR can support three schemes â?? mixed-radix, in-place, and continuous flow â?? at the same time.
Second, a new low-cost and high-speed Reed-Solomon (RS) decoder based on the proposed Simplified Euclidâ??s (OE) algorithm is presented, which can remove the degree computations and comparisons.? The proposed RS decoder has the shortest critical path and the least gate count compared with the existing RS decoders.
Third, a novel Digital Signal Processing (DSP) unit for a Gigabit Ethernet receiver is presented.? The proposed baseline wander (BLW) compensator implemented in a digital domain uses four symbols and can remove even large BLW.? Hence, it improves the MSE performance about 1dB compared with the existing BLW compensator.
Finally, a baseband digital demodulator for Digital Video Broadcasting â?? Satellite second generation (DVB-S2) is presented.? The proposed demodulator can estimate ±5MHz frequency offset at low SNR.? Moreover, the carrier frequency estimator can reduce the hardware complexity by using serial correlators.

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