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November 29, 2009

Mtg: Integrated Circuit Design with Nano-Electro-Mechanical Switches

by @ 6:57 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors
 

THURSDAY January 21, 2010
SCV Solid State Circuits Chapter
Speaker: Prof. Elad Alon, UC-Berkeley
Time: Refreshments at 6:0 PM; Presentation at 6:30 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

No matter how slowly they are allowed to run, digital logic gates implemented with CMOS transistors have a well-defined minimum energy that they must dissipate for each operation they perform.? ? This minimum energy dissipation in CMOS can be traced back to the imperfection of transistors as switches – i.e., that their subthreshold slope is limited by kT/q.? In contrast, switches based on mechanically making or breaking electrical contact can achieve zero leakage and infinite subthreshold slope, and hence may some day enable substantial improvements in energy efficiency.? However, realizing this goal requires that the underlying circuits are tailored to the characteristics of these switches.? Hence, in this talk I will describe such mechanical switch-optimized circuit architectures and then quantify the energy, performance, and area tradeoffs of these designs in comparison to CMOS.

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