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December 18, 2009

Seminar: 3D Interconnect – Shaping Future Technology

by @ 3:14 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, NanoEngineering, Semiconductors
 

FRIDAY January 29, 2010
SCV Electron Devices Chapter
Speakers: experts from academia and the semiconductor industry; to be announced
Time: 9:00 AM to 5:00 PM
Cost: Free. Refereshments and lunch provided
Place: Hyatt Regency Hotel, Santa Clara
RSVP: Through the website link
Web: www.ewh.ieee.org/r6/scv/eds

The demand for higher densities, smaller form factors, and greater functionality, and the quest for developing post-CMOS technologies is spurring ongoing research in a wide variety of wafer-scale integration techniques.? This program brings together experts from academia and the semiconductor industry to examine the state of research into 3D interconnect, development of unit-process and integration, and production qualification.

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