IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

January 1, 2010

Course: Cooling Challenges in 3D Packaging

by @ 8:58 pm. Filed under ALL, BioEngineering, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors

Instructor: Dereje Agonafer, Ph.D., Professor and Director, Elec, MEMS & Nanoelectronics Systems Packaging Center, University of Texas at Arlington
Held at: SEMI-THERM Symposium, Santa Clara Conv’n Ctr
Date: Sunday, Feb. 21, 2010
ABSTRACT: The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging Integrated Circuit packaging requirements. The first part of the course will be a review of electronic packaging based on the instructor’s over 10 years of experience teaching a packaging course. This will be followed by an overview of 3D packaging and an in depth discussion of the thermo/mechanical challenges in stacked packaging based on the author’s recently published papers. Package architectures evaluated in this presentation are rotated stack, staggered stack, stacking with spacers, stacks with thermal vias and package on package. Moving forward in more complex combinations such as stacking logic and memory, there is a desire to include thermal design in the upstream phase concurrently with the architecture design. In order to develop design guidelines for microprocessors based on both thermal and device clock performance, it is necessary to know the characteristics of each functional block on the die, guidelines of which are provided by the architectural team. For better thermal performance, the functional blocks are then repositioned and the resulting maximum temperatures are noted for all the cases. Recent studies at an attempt to a co-architectural design where design optimization is based on both thermal and architectural objectives will also be addressed.
MORE INFORMATION: (see Advance Program)

Comments are closed.

[IEEE S.F. Bay Area Council -] [powered by WordPress .]

SF Bay Area Council


  • 5G (2)
  • ALL (4,702)
  • Antennas & Propagation (5)
  • BioEngineering (675)
  • Blogroll (33)
  • Circuits (16)
  • Communications (1,862)
  • Computers/Software (1,777)
  • Consumer Electronics (103)
  • Control Systems (23)
  • Electrical/Power (1,284)
  • Electronics Design (2,774)
  • Employment (4)
  • Employment opportunities (7)
  • Engineering Mgmt (1,819)
  • Green energy (48)
  • History (7)
  • Industrial Applications (91)
  • Information Theory (13)
  • Instrument and Measurement (1)
  • Magnetics (30)
  • Microwave (8)
  • NanoEngineering (876)
  • Optics/Displays (969)
  • Photonics (31)
  • PhotoVoltaics (4)
  • Product Safety (25)
  • Reliability (37)
  • Robotics and Automation (19)
  • Semiconductors (1,847)
  • Signal Processing (138)
  • Vehicular Technology (16)
  • Women in Engineering (8)
  • Young Professionals (5)

    Support our advertisers:

    Visit our

    Enabling Javascript allows us to show you upcoming conferences in this column.

    For the Firefox browser, select Tools/Options/Content and select "Enable Javascript".

    If you are using Microsoft Internet Explorer you may need to click on the yellow bar above and select 'Allow Blocked Content'. You must then click 'Yes' on the following security warning.


    October 2019
    S M T W T F S
    « May    

    View in Google Calendar

    search blog:

    SUBSCRIBE: Get the e-GRID twice a month by email - upcoming IEEE SF Bay Area meetings, conferences.

    RSS Feed Subscribe to our RSS Feed.

    PUBLICIZE your event to IEEE's membership.

    general links:

    22 queries. 0.429 seconds