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February 10, 2010

Mtg: An Overview of Chip-Level EMC Problems

by @ 1:22 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY March 9, 2010
SCV Electromagnetic Compatibility Chapter
Speaker: Dr. Sergiu Radu, Sun Microsystems, and 2009-2010 IEEE EMC Society Distinguished Lecturer
Time: Light dinner and networking at 5:30 PM; Presentation at 6:30 PM
Cost: Light Dinner and beverages will be served for a fee
Place: Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara
RSVP: Not required
Web: www.ewh.ieee.org/r6/scv/emc

The CPUs and the VLSI chips are the primary sources of electromagnetic noise in all electronic equipments.? Reducing the electromagnetic noise at source level is usually the best and the most economical solution.? The presentation discusses typical interference mechanisms associated with CPU/VLSI, as well as mitigation methods at die-level and package level.? Among the aspects discussed are some power distribution issues, on-die decoupling, package capacitors, routing aspects, the impact of back-bias and forward-bias, and the impact of die-shrinks on the EMI performance of the VLSI chips.
Outline:
1. Introduction. EMI mechanisms for VLSI chips
2. Heatsink effect for large VLSI chips
3. Back-bias impact on EMI
4. Integrated and separated power distribution
5. Noise injection into the PCB
6. Package level improvements for EMI
7. Die level improvements for EMI
8. Second harmonic emissions
9. Power distribution issues
10. Spread Spectrum Clock Generation
11. Die-shrink impact on EMI
12. Conclusions

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