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March 25, 2010

Mtg: Energy-Efficient Design of Digital Circuits

by @ 8:35 am. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

THURSDAY April 15, 2010
SCV Solid State Circuits Chapter, with Circuits and Systems Chapter
Speaker: Prof. Vojin Oklobdzija, IEEE-SSCS Distinguished Lecturer
Time: Refreshments at 6:00 PM, Presentation at 6:30 PM
Cost: small donation to cover food
Place: Qualcomm, Building B, 3165 Kifer Road Santa Clara (this meeting only)
RSVP: not required
Web: ewh.ieee.org/mu/scv-sscs

Techniques for designing and optimizing digital circuits have for a long time been driven by performance.? Power is now the limiting factor to performance.? Logical Effort technique helps to determine transistor sizes for speed as an objective function.? However, it neglects energy issues and fails to provide a guideline when designing with power budget.? Other techniques have been presented which opportunistically improve power, or degrade performance to reduce power.? These approaches do not directly address the true concern of digital designers, which is obtaining the minimal energy for a given performance.? How to make energy-delay trade-offs for the optimal design point is neither well understood nor well defined.? Design space is bound by maximally achievable speed and minimal achievable power.? This presentation addresses the factors impacting optimization of digital circuits, and a framework for the optimal sizing, comparison, and analysis of? energy-efficient designs.

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