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July 16, 2010

Mtg: A Picture is Worth a Thousand (DRC) Rules

by @ 6:20 pm. Filed under Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY July 20, 2010
SCV Nanotechnology Chapter
Speaker: Michael White, Sr Product Manager, Calibre Physical Verification Products, Mentor Graphics
Time: Registration & light lunch at 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: required – from the website
Web: www.ieee.org/nano

New manufacturing issues have a huge effect on how we do IC physical verification at the leading nodes.? Design rule checking has changed from simple one-dimensional spacing and width checks to complex 3D geometrical functions covering a broader context.? This has caused an explosion in DRC deck size and complexity, as designers struggle to code new checks in traditional text-based syntaxes.? We need new, creative ways to perform this analysis in the most efficient way possible.? An approach based on Pattern Matching technology offers intriguing possibilities both for improving the efficiency of full chip simulation and for reducing the difficulty of defining and validating advanced DRC rules.

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