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July 27, 2010

Mtg: 3-D ICs: Motivation, Performance Analysis, Technology and Applications

by @ 3:33 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors

TUESDAY August 10, 2010
SCV Electron Devices Chapter
Speaker: Dr. Krishna C. Saraswat, Dept. of Electrical Engineering, Stanford University
Time: Networking with pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place:National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

For more than 40 years, the performance of silicon integrated circuits has improved at an astonishing rate. The unprecedented growth of the computer and the information technology industry is demanding ULSI circuits with increasing functionality and performance at minimum cost and power dissipation.? Aggressive scaling has introduced some very serious problems for the semiconductor industry.? As the minimum feature size of silicon (Si) CMOS devices shrinks to the nanometer regime, device behavior becomes increasingly complex, due to new physical phenomena and fundamental limitations in material properties.? Scaling of the transistors is becoming increasingly difficult due to diminishing improvement in the on current (ION), increase in off current (IOFF), and thermodynamic limit of the subthreshold swing of 60mV/decade.? These problems may limit the scaling of CMOS devices. The relentless scaling paradigm is also threatened by interconnect limits including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on-chip applications.? Many of these obstacles stem from the physical limitation of copper-based electrical wires, exacerbated by the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in Cu (~40nm).? Additionally, increasing drive for the integration of disparate signals and technologies is introducing various system-on-a-chip (SoC) design concepts, making process integration more difficult.? Finally, the escalating cost of lithography may impose economical limits to scaling. Performance improvement of advanced ULSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced.? This makes it imperative to examine alternate schemes for future continuity of MooreĆ¢??s Law.
One of the techniques that shows promise to overcome this obstacle is the utilization of three-dimensional integrated circuits (3D-ICs). By stacking devices vertically, it is expected that (1) more functionality can fit into a smaller space and (2) the signal delay and power consumption in the interconnect layers will decrease and bandwidth will increase.? This review analyzes the limitations of the existing device and interconnect technologies and presents an alternative 3-D chip design strategy that exploits the vertical dimension to alleviate these problems and to facilitate SoC applications.
A comprehensive analytical treatment of the 3-D ICs will be presented and it will be shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical inter-layer interconnects, significant improvement in performance and reduction in wire-limited chip area can be achieved, without using any other circuit or design innovations.? Furthermore, one of the major concerns in 3-D ICs arising due to increased power density has been analyzed. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips.? Finally, some of the promising technologies, (chip stack packaging, wafer bonding, layer transfer, crystallization, epitaxial growth, etc.) for manufacturing 3-D ICs will be outlined.? Examples of applications of these technologies to real products will be described.

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