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August 29, 2010

Mtg: Ultra-Low-Voltage VLSI Design for Minimum Energy Computing

by @ 4:36 pm. Filed under Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

WEDNESDAY September 1, 2010
SCV Circuits and Systems Chapter
Speaker: Massimo Alioto, Ph.D, Visiting Professor at BWRC — UC-Berkeley
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

In the last years, subthreshold CMOS logic circuits have become very popular in ultra low power applications, which typically constrain the power budget to a few tens of uWs and the supply voltage to a few hundreds of mV.? Designing at such low power and low voltage is challenging and requires a deep understanding of the power delay tradeoff, as well as of the impact of design variables and variability sources on the circuit robustness.
In this talk, a survey of fresh ideas and recent techniques to design and implement subthreshold CMOS logic circuits is presented. Novel circuit models of subthreshold CMOS logic in nanometer technologies are presented to understand its basic properties.? The models are then used to derive design criteria to meet assigned constraints in the power delay design space, as well as to counteract with the issues that arise in nanometer technologies (process/voltage/temperature variations, leakage power, robustness…).? Limitations under nanometer technologies are addressed in the scaling perspective.? Design techniques are discussed at the physical, transistor, gate and system level of abstraction.? Detailed guidelines on how to build ultra low power standard cell libraries are derived, and examples are provided.? A detailed comparison of design flows targeting standard and subthreshold CMOS logic is also presented to understand how to specifically build design flows for ultra low power. Successful designs and state of the art chips are presented to gain a clear understanding of the state of the art, and which direction the research is moving to.

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