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December 7, 2007

Mtg: Educating Engineers in Advanced Silicon Processes

by @ 6:38 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY December 19
SCV Education Chapter
Speaker: Dr. Kris Verma
Time: dinner at 6:30 PM, Presentation at 7:00 PM
Cost: none
Place: Silicon Valley Technical Institute; 1762 Technology Dr., Suite 227, San Jose
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/es

 

During the last two decades, the Semiconductor Industry model? has changed from Vertical (Design, Fab, Test, and Packaging) under one IDM (Integrated Device Manufacturer) to a Horizontal model (Fabless Design Houses, IP developers, Wafer Mega Foundries, and subcontractors for test and assembly) under different companiesâ?? management. ? This new business model? has created good business opportunities and growth, but created? some challenges to young? engineers for learning opportunities in various areas in the same company.? The problem has been further compounded, since most of Silicon Process development (R&D) work and Manufacturing have now moved to Asia.?

Due to very aggressive process scaling over the last 10 years (5 nodes in 10 years), nanoscale node process variations and? impact on Design yield have forced designers and product engineers to learn Silicon Processes for successful product introduction to manufacturing.? Extensive process simulations and TCAD tools expertise became necessary. ? This process knowledge allows them to interact with the Mega foundries (in ASIA) effectively.

This talk will cover advanced Silicon Processes (ITRS, NanoCMOS nodes, Life after CMOS) and some ideas on how to educate a new generation of engineers in this exciting Industry.

 

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